N-way memory barrier operation coalescing

A computing system, comprising:

• a memory;
• and
• a parallel processing subsystem coupled to the memory and comprising:
• an instruction scheduling unit configured to:
• issue for execution a first memory barrier instruction for a first thread group that includes multiple parallel execution threads;
• issue for execution, subsequent to the first memory barrier instruction, a first set of memory transactions and a second memory barrier instruction for at least a second thread group that includes multiple execution threads;
• block the execution of memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order;
• block the execution of memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order;
• and
• release both the first memory barrier instruction to allow execution of the memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order and the second memory barrier instruction to allow execution of the memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order when an acknowledgement signal is received;
• a memory management unit configured to process memory transactions and memory barrier instructions;
• and
• a memory barrier instruction execution unit that is configured to:
• receive the first memory barrier instruction;
• receive the first set of memory transactions and the second memory barrier instruction;
• coalesce the first memory barrier instruction and the second memory barrier instruction to generate a coalesced memory barrier instruction;
• tag each transaction in the first set of memory transactions with a first coalescing index associated with the coalesced memory barrier instruction to generate tagged memory commands;
• and
• combine the tagged memory commands and the coalesced memory barrier instruction to generate a tagged memory command stream.

A processing subsystem comprising:

• an instruction scheduling unit configured to:
• issue for execution a first memory barrier instruction for a first thread group that includes multiple parallel execution threads;
• issue for execution, subsequent to the first memory barrier instruction, a first set of memory transactions and a second memory barrier instruction for at least a second thread group that includes multiple execution threads;
• block the execution of memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order;
• block the execution of memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order;
• and
• release both the first memory barrier instruction to allow execution of the memory transactions for the first thread group that are subsequent to the first memory barrier instruction in program order and the second memory barrier instruction to allow execution of the memory transactions for the second thread group that are subsequent to the second memory barrier instruction in program order when an acknowledgement signal is received;
• a memory management unit configured to process memory transactions and memory barrier instructions;
• and
• a memory barrier instruction execution unit that is configured to:
• receive the first memory barrier instruction;
• receive the first set of memory transactions and the second memory barrier instruction;
• coalesce the first memory barrier instruction and the second memory barrier instruction to generate a coalesced memory barrier instruction
• tag each transaction in the first set of memory transactions with a first coalescing index associated with the coalesced memory barrier instruction to generate tagged memory commands;
• and
• combine the tagged memory commands and the coalesced memory barrier instruction to generate a tagged memory command stream.