Method of fabricating a charge-trapping gate stack using a CMOS process flow
AssigneeCypress Semiconductor Corporation
InventorsKrishnaswamy Ramkumar, Hui-Mei (Mei) Shih
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Abstract
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
Claims20
A method comprising:
- forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric over the substrate and a charge-trapping layer over the tunneling dielectric;
- forming a first cap layer comprising an oxide over the dielectric stack;
- forming a second cap layer comprising a nitride over the first cap layer;
- patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device in a first region of the substrate;
- removing the second cap layer;
- and
- performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer.
A method comprising:
- forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric over the substrate and a charge-trapping layer over the tunneling dielectric;
- forming a first cap layer comprising an oxygen-rich-nitride over the dielectric stack;
- forming a second cap layer comprising a nitride over the first cap layer;
- patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device in a first region of the substrate;
- removing the second cap layer;
- and
- performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer.
A method comprising:
- forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric over the substrate and a charge-trapping layer over the tunneling dielectric;
- growing a first cap layer comprising a thin oxide over the dielectric stack in a first chamber of a cluster tool;
- forming a second cap layer comprising a nitride over the first cap layer in a second chamber of the cluster tool;
- forming a sacrificial oxide comprising a high-temperature-oxide (HTO) using a radical oxidation process over the second cap layer in a third chamber of the cluster tool;
- patterning the sacrificial oxide, first and second cap layers and the dielectric stack to form a gate stack of a memory device in a first region of the substrate;
- removing the sacrificial oxide and second cap layer;
- and
- performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer.
Dependencies are inferred from the claim text.