US 8,988,173 B2Granted

Differential negative impedance converters and inverters with variable or tunable conversion ratios

AssigneeHRL Laboratories, LLC

InventorsDonald A. Hitko, Carson R. White, Michael W. Yung, David S. Matthews, Susan L. Morton, Jason W. May, Joseph S. Colburn

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Abstract

A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).

A non-Foster circuit comprising:

two differential pairs of transistors that are cross-coupled, each transistor of said two differential pairs of transistors having a pair of current carrying electrodes and a control electrode, the control electrodes of the transistors in a first one of said two differential pairs of transistors being coupled to one of the current carrying electrodes of the transistors in a second one of said two differential pairs of transistors, the control electrodes of the transistors in the second one of said two differential pairs of transistors being coupled to one of the current carrying electrodes of the transistors in the first one of said two differential pairs of transistors;
a load immittance coupled to one of the current carrying electrodes of each of the transistors in said first one of said differential pair of transistors and a first control resistance coupled to another one of the current carrying electrodes of each of the transistors in said first one of said differential pair of transistors;
current sources for supplying a flow of current to at least one of the current carrying electrodes of each of the transistors in said two differential pairs of transistors;
two common-mode feedback networks, each common-mode feedback network being coupled to current carrying electrodes of the transistors of one of the two differential pairs of transistors;
and
terminals across which a desired immittance is generated, the terminals being coupled to one of the current carrying electrodes of each of the transistors in said second one of said differential pair of transistors and a second control resistance coupled to another one of the current carrying electrodes of each of the transistors in said second one of said differential pair of transistors, a function based at least in part on a product of the resistances of the first and second control resistances setting a conversion ratio between the load immittance and the desired immittance.

3 more elements

Facts

Application

13/441,730Filed 6 Apr 2012 · us provisional application

Priority

7 Apr 2011

Published

US 2012/0256709 A111 Oct 2012

Granted

24 Mar 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03H 11/10
Frequency selective two-port networks: using negative impedance converters
H03F 1/56
Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements: modifications of…
H03H 11/44
Impedance converters: negative impedance converters
H03H 11/48
One-port networks: simulating reactances

Abstract

Claims37