Method and system for operating a communication circuit configurable to support one or more data rates

A method for operating a communication circuit, comprising:

• at a first PCS transmit module of a transmitter of a first device, providing a stream of information arranged in packets at a first data rate;
• at said first PCS transmit module, striping said stream of information into one or more substreams of information delivered over one or more channels, wherein each of said channels operate at a second data rate equal to or lower than said first data rate;
• at said first PCS transmit module, periodically adding an alignment marker to each substream of information;
• and
• performing forward error correction (FEC) on each substream, wherein one or more FEC encoding modules of a plurality of FEC encoding modules are configured to support said first PCS transmit module, wherein each of said plurality of FEC modules operate at approximately said second data rate;
• providing a second PCS transmit module at said transmitter, wherein said second PCS transmit module operates at a third data rate greater than said second data rate, and wherein one or more of said plurality of FEC modules are configurable to support said second PCS transmit module operating at said third data rate;
• at a receiver of said first device, configuring a plurality of FEC decoding modules to receive one or more substreams of information transmitted from a second device operating at said second data rates;
• at each of said one or more FEC decoding modules, performing error correction;
• at an alignment module of said receiver, performing block alignment on said one or more substreams of information;
• and
• at a deskew module of said receiver, performing deskew between on said one or more substreams of information received by said receiver.

A communication circuit, comprising:

• a receiver of a first device for receiving packets of information over one or more channels corresponding to a selected first or second PCS module from a transmitter of a second device, wherein said first PCS module operates at a first data rate of approximately 10 gigabits per second, and wherein said second PCS module operates at a second data rate of approximately 40 gigabits per second;
• wherein said receiver comprises a plurality of FEC decoding modules, each operating at said specified data rate of approximately 10 gigabits per second, wherein one or more FEC decoding modules are configured to receive said packets of information from one or more FEC encoding modules of said transmitter of said second device over said one or more channels;
• and
• wherein said receiver comprises a BER state machine in a PCS receive module for determining a high bit error rate when discovering a predetermined number of errored SYNC blocks out of a 125 microsecond window from said packets of information.