System and method for avoiding error mechanisms in layered iterative decoding

A decoder for decoding encoded data, the encoded data comprising a plurality of log-likelihood ratios (LLRs), each of the plurality of LLRs representing one of a plurality of bits of a codeword encoded using a parity check matrix having a plurality of layers, the decoder comprising circuitry for:

• performing iterative decoding of the plurality of LLRs utilizing a layered iterative decoding process following a first processing order of the plurality of layers of the parity check matrix to provide a codeword estimate of the encoded codeword until the codeword estimate is determined to be a valid codeword or until a maximum number of iterations of the iterative decoding is reached using the first processing order of the plurality of layers of the parity check matrix;
• and
• if a maximum number of iterations of the iterative decoding is reached and the codeword estimate is not determined to be a valid codeword, performing iterative decoding of the plurality of LLRs utilizing a layered iterative decoding process following a second processing order of the plurality of layers of the parity check matrix, wherein the second processing order of the plurality of layers of the parity check matrix that is a different processing order than the first processing order of layers, to provide a codeword estimate of the encoded codeword until the codeword estimate is determined to be a valid codeword or until the maximum number of iterations of the iterative decoding is reached using the second processing order of the plurality of layers of the parity check matrix.

An LDPC decoder for decoding low-density parity check (LDPC) encoded data, the LDPC encoded data comprising a plurality of log-likelihood ratios (LLRs), each of the plurality of LLRs representing one of a plurality of bits of an LDPC codeword encoded using a parity check matrix having a plurality of layers, the decoder comprising:

• decoding circuitry for performing iterative decoding of the plurality of LLRs utilizing a layered iterative decoding process following a first processing order of the plurality of layers of the parity check matrix to provide a codeword estimate of the encoded codeword until the codeword estimate is determined to be a valid codeword or until a maximum number of iterations of the iterative decoding is reached using the first processing order of the plurality of layers of the parity check matrix;
• and if a maximum number of iterations of the iterative decoding is reached and the codeword estimate is not determined to be a valid codeword, performing iterative decoding of the plurality of LLRs utilizing a layered iterative decoding process following a second processing order of the plurality of layers of the parity check matrix, wherein the second processing order of the plurality of layers of the parity check matrix is a different processing order than the first processing order of layers, to provide a codeword estimate of the encoded codeword until the codeword estimate is determined to be a valid codeword or until the maximum number of iterations of the iterative decoding is reached using the second processing order of the plurality of layers of the parity check matrix;
• and
• a layer ordering circuit coupled to the decoding circuitry, the layer ordering circuit for determining the first processing order of the plurality of layers of the parity check matrix and for determining the second processing order of the plurality of layers of the parity check matrix.