# US 8,975,948 B2 · Wide common mode range transmission gate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,975,948 B2 - Document ID: US8975948B2 - Status: Granted - Kind: B2 - Application number: 13/677,858 - Filed: 2012-11-15 - Published: 2014-05-15 - Granted: 2015-03-10 - Earliest claimed: 2012-11-15 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Sigfredo Emanuel Gonzalez Diaz - Web page: https://patentgrep.com/patent/US8975948B2 ## CPC - H03K 17/0822: {in field-effect transistor switches} - H03K 17/08122: {in field-effect transistor switches} - H03K 17/162: {without feedback from the output circuit to the control circuit} - H03K 17/6874: {in a symmetrical configuration} - H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) - H03K 2217/0054: Gating switches, e.g. pass gates - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to the gate's output and protects the transistors' gate oxide in cases of high input signals. An array of matched transistors are arranged to be biased by a voltage input node and with a current source configured to provide a bias current across individual transistors of the array of matched transistors. A current sink is configured to sink the bias current across the individual transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors. A different set of transistors is configured to provide a signal path for an analog input signal. ## Claims ### Claim 1 An apparatus comprising: an analog input line; an analog output line; a first transistor having a first drain electrically connected to the analog input line, a first gate electrically connected to a voltage input node, and a first source electrically connected to an analog signal node; a second transistor; a third transistor; wherein the second transistor and the third transistor are electrically connected between the voltage input node and the analog signal node wherein: the second transistor has a second drain and a second gate electrically connected to the voltage input node, and the third transistor has a third drain and third gate both electrically connected to a second source of the second transistor and a third source electrically connected to the analog signal node; a fourth transistor having a fourth source electrically connected to the analog signal node, a fourth gate electrically connected to the voltage input node, and a fourth drain electrically connected to the analog output line; a current source electrically connected to provide a bias current into the voltage input node; a current sink electrically connected to sink current from the analog signal node. ### Claim 2 (depends on 1) The apparatus of claim 1 further comprising a diode having an anode electrically connected to the analog signal node and having a cathode electrically connected to the voltage input node. ### Claim 3 (depends on 1) The apparatus of claim 1 further comprising: a first transistor diode having an anode electrically connected to the first source and a first body of the first transistor and a cathode electrically connected to the first drain; and a fourth transistor diode having an anode electrically connected to the fourth source and a fourth body of the fourth transistor and a cathode electrically connected to the fourth drain. ### Claim 4 (depends on 1) The apparatus of claim 1 wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are high voltage matched transistors. ### Claim 5 (depends on 1) The apparatus of claim 1 wherein the current sink is configured to sink current used to bias the second transistor and the third transistor to allow the analog signal node's signal to be determined by a signal received by the analog input line. ### Claim 6 (depends on 1) The apparatus of claim 1 further comprising low dropout regulator circuitry comprising: a fifth transistor having a fifth drain electrically connected to a low dropout regulator input line, a fifth gate electrically connected to the analog output line, and a fifth source electrically connected to a low dropout regulator output line and a voltage divider; an error amplifier circuit electrically connected to the voltage divider and configured to compare a signal from the voltage divider to a reference voltage and to output a feedback signal to the analog input line. ### Claim 7 A transmission gate circuit apparatus comprising: a self-biased gate drive configured to provide constant gate biasing to an array of matched transistors; wherein the self-biased gate drive includes: a current source configured to provide a bias current across individual transistors of the array of matched transistors; a current sink configured to sink the bias current across the individual transistors of the array of matched transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors; a different set of transistors from the individual transistors of the array of matched transistors configured to provide a signal path for an analog input signal received at one of the different set of transistors to be output as an analog output signal from another one of the different set of transistors to be biased at a multiple of a gate-to-source voltage for the different set of transistors, wherein: the individual transistors of the array of matched transistors include a second transistor and third transistor; the different set of transistors includes a first transistor and a fourth transistor; the first transistor has a first drain electrically connected to an analog input line configured to receive the analog input signal, a first gate electrically connected to the voltage input node, and a first source electrically connected to an analog signal node; the second transistor and the third transistor are electrically connected between the voltage input node and the analog signal node wherein: the second transistor has a second drain and a second gate electrically connected to the voltage input node, and the third transistor has a third drain and third gate both electrically connected to a second source of the second transistor and a third source electrically connected to the analog signal node; a fourth transistor having a fourth source electrically connected to the analog signal node, a fourth gate electrically connected to the voltage input node, and a fourth drain electrically connected to the analog output line. ### Claim 8 (depends on 7) The transmission gate circuit apparatus of claim 7 further comprising: a first transistor diode having an anode electrically connected to the first source and a first body of the first transistor and a cathode electrically connected to the first drain; and a fourth transistor diode having an anode electrically connected to the fourth source and a fourth body of the fourth transistor and a cathode electrically connected to the fourth drain. ### Claim 9 (depends on 7) The apparatus of claim 7 further comprising low dropout regulator circuitry comprising: a fifth transistor electrically connected to a low dropout regulator input line, to receive an analog output signal from the self-biased gate drive, and to a low dropout regulator output line with a voltage divider; an error amplifier circuit electrically connected to the voltage divider and configured to compare a signal from the voltage divider to a reference voltage and to output a feedback signal to the self-biased gate drive.