Integrated circuit having an edge passivation and oxidation resistant layer and method

A method for producing an integrated circuit having a semiconductor component arrangement, comprising:

• forming a semiconductor material region having a surface region;
• forming an arrangement of one or more semiconductor components in a central region of the semiconductor material region thereby laterally subdividing the semiconductor material into the central region and an edge region being for the electrical edge termination of the arrangement of the one or more semiconductor components;
• forming a passivation layer region on the surface region of the semiconductor material region in the edge region thereof, the passivation layer region being configured to realize a field distribution at the edge of the semiconductor component arrangement, wherein the passivation layer region is formed with a base layer including hydrogen containing amorphous carbon at the bottom and directly adjoining the semiconductor material region;
• forming an oxide layer region as a protection against oxidation on and in direct contact with the surface region of the semiconductor material region in the edge region of the semiconductor material region;
• forming the passivation layer region between the oxide layer region and the central region;
• forming the oxide layer region or a part of the oxide layer region in direct contact with a channel stopper region, the channel stopper region being formed as a doped zone of a first conductivity type in the surface region of the semiconductor material region or as a plurality of doped zones of the first conductivity type in the surface region of the semiconductor material region;
• forming a VLD zone having a varying doping of a second conductivity type decreasing toward the edge of the semiconductor material region in the surface region of the semiconductor material region in the transition between the central region and the edge region of the semiconductor material region;
• forming a first contact metallization at a first surface of the semiconductor material region;
• and
• forming a second contact metallization at a second surface of the semiconductor material region opposite to the first surface.