Device including two power semiconductor chips and manufacturing thereof

A device, comprising:

• a first MOSFET power semiconductor chip having a first face and a second face opposite the first face, wherein a source contact pad and a gate contact pad are arranged on the first face and a drain contact pad is arranged on the second face, wherein a first metal layer is attached to the second face of the first MOSFET power semiconductor chip;
• and
• a second MOSFET power semiconductor chip having a first face and a second face opposite the first face, wherein a source contact pad and a gate contact pad are arranged on the first face and a drain contact pad is arranged on the second face,
• wherein the first and second MOSFET power semiconductor chips are arranged one above another,
• wherein the first face of the first MOSFET power semiconductor chip faces toward the first face of the second MOSFET power semiconductor chip,
• wherein the first MOSFET power semiconductor chip and the second MOSFET power semiconductor chip are coupled to each other in a half-bridge circuit, and
• wherein the first metal layer electrically couples the drain contact pad to the first MOSFET power semiconductor chip to the source contact pad of the second MOSFET power semiconductor chip.

A device, comprising:

• a first semiconductor chip having a first face and a second face opposite the first face, wherein a first contact pad and a second contact pad are arranged on the first face and a third contact pad is arranged on the second face, and wherein a first metal layer is attached to the second face of the first semiconductor chip;
• and
• a second semiconductor chip having a first face and a second face opposite the first face, wherein a first contact pad and a second contact pad are arranged on the first face and a third contact pad is arranged on the second face,
• wherein the first and second semiconductor chips are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction,
• wherein the first semiconductor chip is located laterally at least partially outside of an outline of the second semiconductor chip, and
• wherein the first metal layer electrically couples the third contact pad of the first semiconductor chip to the first contact pad of the second semiconductor chip.