Memory circuit incorporating radiation-hardened memory scrub engine

An integrated circuit comprising:

• a first memory array comprising a first plurality of data groups, each such data group including a respective plurality of data bits;
• a second memory array comprising a second plurality of data groups, each such data group including a plurality of data bits;
• a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array, said first EDAC circuit comprising spatially redundant circuitry;
• a second error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the second memory array, said second EDAC circuit comprising spatially redundant circuitry;
• and
• an output circuit configured to present at least a portion of a data group from the first memory array and at least a portion of a data group from the second memory array together as a single memory word;
• wherein the first EDAC circuit and the second EDAC circuit each includes at least one of buried guard ring (BGR) structures and parasitic isolation device (PID) structures;
• wherein the spatially redundant circuitry of the first EDAC circuit and the second EDAC circuit comprises dual interlocked storage cell (DICE) circuits;
• and
• wherein the first EDAC circuit is operable independently of the second EDAC circuit.

An integrated circuit comprising:

• a memory circuit including multiple memory banks, each memory bank having a respective memory word depth and memory word width, each memory word comprising data bits and associated check bits;
• a scrub engine configured to access memory words in said multiple memory banks, detect a bit error in a given memory word, correct the bit error and re-write the given memory word with the corrected bit, all without conveying the data bits or check bits of the memory word to an external interface of the integrated circuit;
• wherein the memory circuit is operable with an external word width greater than that of a single bank;
• wherein the scrub engine includes spatially redundant circuitry and further includes at least one of buried guard ring (BGR) structures and parasitic isolation device (PID) structures;
• and
• wherein the spatially redundant circuitry of the scrub engine includes dual interlocked storage cell (DICE) circuits.

An integrated circuit comprising:

• a memory circuit including two logical memory banks, each logical memory bank respectively comprising M memory words, each memory word respectively comprising N data bits and P associated check bits, each logical memory bank further comprising a respective scrub engine;
• wherein the memory circuit is operable as a 2M×N array or as a M×2N array;
• wherein each respective scrub engine includes spatially redundant circuitry and further includes at least one of buried guard ring (BGR) structures and parasitic isolation device (PID) structures;
• and
• wherein the spatially redundant circuitry comprises dual interlocked storage cell (DICE) circuits.

An integrated circuit comprising:

• a first memory array comprising a first plurality of data groups, each such data group including a respective plurality of data bits;
• a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array, said first EDAC circuit comprising spatially redundant circuitry;
• a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein, said first scrub circuit comprising spatially redundant circuitry;
• a second memory array comprising a second plurality of data groups, each such data group including a plurality of data bits;
• a second error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the second memory array, said second EDAC circuit comprising spatially redundant circuitry;
• and
• a second scrub circuit configured to access in a sequence each of the second plurality of data groups to correct any detected errors therein, said second scrub circuit comprising spatially redundant circuitry;
• wherein the first scrub circuit and the first EDAC circuit are operable independently of the second scrub circuit and the second EDAC circuit;
• wherein the first EDAC circuit and the first scrub circuit each includes buried guard ring (BGR) structures and parasitic isolation device (PID) structures;
• wherein the spatially redundant circuitry comprises dual interlocked storage cell (DICE) circuits;
• and
• wherein the BGR structure comprises:
• a substrate having a region of a first conductivity type and a first substrate impurity concentration;
• a first well having the first conductivity type, wherein the first well includes a first well contact region;
• a second well having a second conductivity type opposite the first conductivity type;
• and
• a buried layer of the first conductivity type and having a buried layer impurity concentration greater than the first substrate impurity concentration, said buried layer disposed within the substrate below the first and second wells and extending continuously beneath the first and second wells.