Modifying work function in PMOS devices by counter-doping
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun-Yi Lee, Harry-Hak-Lay Chuang, Ping-Wei Wang, Kong-Beng Thei
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Abstract
A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
Claims20
A structure comprising:
- a semiconductor substrate;
- a first p-type transistor device in a memory region in the semiconductor substrate, the first p-type transistor device comprising a first gate electrode;
- and
- a second p-type transistor device in a peripheral circuit, the second p-type transistor device comprising a second gate electrode,
- wherein a work function of the first gate electrode is different from a work function of the second gate electrode, and wherein a saturation voltage of the first p-type transistor device is greater than 10% more than a saturation voltage of the second p-type transistor device.
A structure comprising:
- a first gate stack of a first transistor, the first gate stack being in a logic cell region on a substrate, the first gate stack comprising a first high-k gate dielectric and a first gate electrode on the first high-k gate dielectric;
- and
- a second gate stack of a second transistor, the second gate stack being in a peripheral region on the substrate, the second gate stack comprising a second high-k gate dielectric and a second gate electrode on the second high-k gate dielectric, the first transistor and the second transistor being a same first transistor type, a work function of the first transistor being greater than a work function of the second transistor.
A structure comprising:
- a first p-type transistor in a logic cell region on a substrate, the first p-type transistor comprising a first gate electrode on a first high-k gate dielectric, the first gate electrode comprising a metal;
- a second p-type transistor in a peripheral region on the substrate, the second p-type transistor comprising a second gate electrode on a second high-k gate dielectric, the second gate electrode comprising a metal, the first gate electrode comprising a greater concentration of a n-type impurity than the second gate electrode, the first p-type transistor having a higher work function than the second p-type transistor;
- a first n-type transistor in the logic cell region on the substrate;
- and
- a second n-type transistor in the peripheral region on the substrate.
Dependencies are inferred from the claim text.