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US 8,966,425 B1Granted
Clock tree generation and routing
AssigneePulsic Limited
InventorsRobert Eisenstadt, Mark Waller, Tim Parker, Mark Williams, Jeremy Birch, Graham Balsdon, Fumiako Sato
Life of this patent
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Abstract
A technique generates small scale clock trees using a spine-based architecture (using spine routing) while also using clustered placement. Techniques are used to control clock sink cluster contents in order to minimize clock skew, minimize clock buffer count, and minimize use of routing resources. This approach also provides the user with ample structure and control to customize small efficient clock trees, and can also reduce clock power consumption.
Claims20
A method comprising:
- using at least one processor, using top level routing and buffering guides to control the top level clock signal implementation comprising:
- identifying N clock pins to couple;
- calculating a route area to comprise the positions the N clock pins;
- routing a spine interconnect extending in a first direction a length of the route area in the first direction;
- coupling the spine interconnect to a prebuffer that is coupled to a clock input pin;
- and
- routing N stitching interconnects in a second direction to couple each of the N pins to the spine interconnect,
- wherein each of the N stitching interconnects comprises at least one buffer, and
- the first direction is orthogonal to the second direction.
6 more elements
A method comprising:
- using at least one processor, using netlist-aware placement of clock sinks to drive clock sink placement, which optimizes local sink clustering and buffering comprising:
- identifying N and M clock pins to couple;
- routing a first spine interconnect extending in a first direction a length of the route area in the first direction;
- coupling the first spine interconnect to a prebuffer that is coupled to a clock source;
- routing a second spine interconnect extending in a first direction a length of the route area in the first direction;
- coupling the first spine interconnect through at least a first buffer to drive the second spine interconnect;
- routing N stitching interconnects in a second direction to couple each of the N pins to the first spine interconnect,
- wherein each of the N stitching interconnects comprises at least one buffer, and
- the first direction is orthogonal to the second direction;
- and
- routing M stitching interconnects in the second direction to couple each of the M pins to the second spine interconnect,
- wherein each of the M stitching interconnects comprises at least one buffer.
9 more elements
Dependencies are inferred from the claim text.