Metastability error detection and correction system and method for successive approximation analog-to-digital converters

A system for detection and correction of metastability errors in a conversion of a sampled analog signal by a successive approximation analog to digital converter, comprising:

• a comparator unit for the successive approximation analog to digital converter having an output coupled to a successive approximation register of the successive approximation analog to digital converter, said comparator unit initiating a comparison of a sampled analog signal with a quantization level reference established by the successive approximation analog to digital converter responsive to a comparator clocking signal, and subsequently outputting a signal corresponding to said comparator unit latching a bit value respectively for each of a plurality of sequential bit conversion states of the successive approximation analog to digital converter, said comparator unit outputting said latched bit value to the successive approximation register;
• and
• a metastability detection and correction circuit coupled to the successive approximation register, the logic state machine and a clock generator, said metastability detection and correction circuit being further coupled to said comparator unit for detecting a metastable event therein and outputting bit values received from the successive approximation register responsive to an absence of a metastable event and output of selected bit values responsive to detection of at least one metastable event within a processing cycle of the successive approximation analog to digital converter to provide an output bit value within each conversion time period of the processing cycle of the successive approximation analog to digital converter.

A method of detecting and correcting metastability errors in a successive approximation analog to digital converter, comprising the steps of:

• sampling an analog voltage;
• sequentially establishing a quantization level reference for each of a plurality of bit conversion states of a processing cycle using a successive approximation algorithm;
• using a comparator to sequentially perform a clocked comparison between said sampled analog voltage and said quantization level reference for each said bit conversion state;
• determining whether the comparator has latched an output bit value within a portion of a conversion time period and defining an occurrence of a metastable event for a respective bit conversion state responsive to a failure of the comparator to latch an output bit value within the portion of the conversion time period, connecting a logic circuit to the comparator for output of a logic signal responsive to detecting said latching of an output bit value, and using a clocked flip flop for each bit conversion state configured to receive said logic signal and a timing signal for detecting a presence of said logic signal by a conclusion of said portion of a conversion time period and detecting said metastable event responsive to an absence thereof;
• and
• setting a value of an output bit corresponding to said respective bit conversion state coincident with said metastable event to a logic one and each less significant bit value sequentially thereafter within the processing cycle to a logic zero.