Laminate stacked capacitor, circuit substrate with laminate stacked capacitor and semiconductor apparatus with laminate stacked capacitor

A circuit substrate, comprising:

• a multilayer structure including a plurality of resin build-up layers, a plurality of external terminals including a power supply terminal and a ground terminal on a first side thereof, and a plurality of electrode pads including a power supply pad and a ground pad on a second side opposite to the first side;
• and
• a capacitor embedded in one of the resin build-up layers, the capacitor including:
• a metal base;
• a plurality of ceramic capacitor dielectric layers disposed on top of one another on the base, the capacitor dielectric layers including a first capacitor dielectric layer, a second capacitor dielectric layer adjacent to the first capacitor dielectric layer, and a third capacitor dielectric layer adjacent to the second capacitor dielectric layer at the opposite side to the first capacitor dielectric layer;
• a first copper electrode pattern and a first copper via-plug with a space therebetween between the first capacitor dielectric layer and the second capacitor dielectric layer;
• a second copper electrode pattern and a fourth copper via-plug with a space therebetween between the second capacitor dielectric layer and the third capacitor dielectric layer;
• and
• a second via-plug and a third via-plug in the second capacitor dielectric layer,
• wherein
• the first copper electrode pattern opposes the second copper electrode pattern with the second capacitor dielectric layer therebetween,
• the first copper via-plug is electrically connected to the second copper electrode pattern through the third via-plug,
• the fourth copper via-plug is electrically connected to the first copper electrode pattern through the second via-plug, and
• the first copper electrode pattern and the second copper electrode pattern are electrically connected to a first terminal and a second terminal, respectively.

A semiconductor apparatus, comprising:

• a circuit substrate including a multilayer structure of a plurality of resin build-up layers, having external terminals including a power supply terminal and a ground terminal on a first side thereof, and a plurality of electrode pads including a power supply pad and a ground pad on a second side opposite to the first side;
• a semiconductor chip having a plurality of electrodes, mounted on the circuit substrate by flip chip bonding in such a manner that the electrodes are connected to the corresponding electrode pads;
• and
• a capacitor embedded in one of the resin build-up layers, the capacitor including:
• a metal base;
• a plurality of ceramic capacitor dielectric layers disposed on top of one another on the base, the capacitor dielectric layers including a first capacitor dielectric layer, a second capacitor dielectric layer adjacent to the first capacitor dielectric layer, and a third capacitor dielectric layer adjacent to the second capacitor dielectric layer at the opposite side to the first capacitor dielectric layer;
• a first copper electrode pattern and a first copper via-plug with a space therebetween between the first capacitor dielectric layer and the second capacitor dielectric layer;
• a second copper electrode pattern and a fourth copper via-plug with a space therebetween between the second capacitor dielectric layer and the third capacitor dielectric layer;
• and
• a second via-plug and a third via-plug in the second capacitor dielectric layer,
• wherein
• the first copper electrode pattern opposes the second copper electrode pattern with the second capacitor dielectric layer therebetween,
• the first copper via-plug is electrically connected to the second copper electrode pattern through the third via-plug,
• the fourth copper via-plug is electrically connected to the first copper electrode pattern through the second via-plug, and
• the first copper electrode pattern and the second copper electrode pattern are electrically connected to a first terminal and a second terminal, respectively.