Digital-to-analogue converter and neuromorphic circuit using such a converter

A neuromorphic circuit comprising

• a neuronal network with each neuron identified by a neuron address in the network, each neuron being able to receive and process at least one input signal then later emit to an output of the neuron a signal representing an event which occurs inside the neuron,
• a programmable memory which can be addressed by the neuron address of a neuron having emitted an event signal representing a result of an activity of the neuron, the programmable memory containing at this address a digital datum comprising one or more post-synaptic neuron addresses and a respective post-synaptic weight associated with each post-synaptic address,
• reading means for extracting from the memory the datum relating to a neuron, after this neuron has emitted an event signal representing a result of the activity of the neuron, and
• a digital-to-analogue converter for applying, to the input of a post-synaptic neuron identified by an address contained in the datum, a current pulse, the amplitude of which represents the post-synaptic weight associated with this address in the datum,
• wherein the digital-to-analogue converter comprises
• at least one set of several transistors of identical nominal geometrical characteristics but of dispersed current-voltage characteristics such that, when a constant gate-source voltage is applied to the different transistors, a current that is variable as a function of the dispersion circulates in the transistor,
• a digital look-up table having a digital input and a selection output for selecting, as a function of the digital input, a transistor or a group of transistors from the set,
• a current output supplying the current delivered by the selected transistor or group of transistors, all receiving a nominal gate-source voltage, and
• means for loading into the digital look-up table determined data determining the selection of transistors, as a function of real measured current-voltage characteristics of the different transistors of the set, the look-up table being different from the one which would be obtained if the transistors all had said nominal characteristics.