Multi-threaded processing with hardware accelerators
AssigneeLSI Corporation
InventorsDeepak Mital, William Burroughs, Eran Dosh, Eyal Rosin
Life of this patent
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AssigneeLSI Corporation
InventorsDeepak Mital, William Burroughs, Eran Dosh, Eyal Rosin
Estimating the term…
Described embodiments process multiple threads of commands in a network processor. One or more tasks are generated corresponding to each received packet, and the tasks are provided to a packet processor module (MPP). A scheduler associates each received task with a command flow. A thread updater writes state data corresponding to the flow to a context memory. The scheduler determines an order of processing of the command flows. When a processing thread of a multi-thread processor is available, the thread updater loads, from the context memory, state data for at least one scheduled flow to one of the multi-thread processors. The multi-thread processor processes a next command of the flow based on the loaded state data. If the processed command requires operation of a co-processor module, the multi-thread processor sends a co-processor request and switches command processing from the first flow to a second flow.
A method of processing multiple threads of commands in a network processor having a plurality of processing modules and at least one shared memory:
A non-transitory machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of processing multiple threads of commands in a network processor having a plurality of processing modules and at least one shared memory:
A module packet processor (MPP) of a network processor having a plurality of processing modules and at least one shared memory, wherein the network processor generates one or more tasks corresponding to each packet received by the network processor, the MPP comprising:
Dependencies are inferred from the claim text.