Assist thread for injecting cache memory in a microprocessor

A method for reducing memory latency associated with a main thread in a data processing system including a higher level cache having a lower access latency and a lower level cache having a higher access latency, the method comprising:

• a processor generating a main thread and an assist thread from a source code object, wherein the assist thread includes a smaller subset of the instructions in the main thread, wherein the subset of instructions in the assist thread includes memory access instructions, those arithmetic instructions required to resolve memory references in the memory access instructions, and any branch instruction required to determine whether a memory access instruction among the memory access instructions is to be executed;
• the processor scheduling the assist thread to execute simultaneously with the main thread;
• the processor constraining execution of the main thread relative to the assist thread, such that each instruction in the main thread having a corresponding instruction in the assist thread always executes after the corresponding instruction in the assist thread;
• and
• the processor making a memory access requested by an instruction of the assist thread directly to the lower level cache without first accessing the higher level cache and making a corresponding memory access requested by an instruction in the main thread to the higher level cache.

A data processing system, comprising:

• a multi-level cache memory hierarchy including at least a higher level cache having a lower access latency and a lower level cache having a higher access latency;
• a main processor coupled to access the multi-level cache memory, wherein the main processor simultaneously executes a main thread and an assist thread, wherein the assist thread is derived from a same source code object as the main thread and contains a smaller subset of the instructions in the main thread, wherein the subset of instructions executed in the assist thread includes memory access instructions, those arithmetic instructions required to resolve memory references in the memory access instructions, and any branch instruction required to determine whether a memory access instruction among the memory access instructions is to be executed, and wherein the main processor makes memory accesses indicated by the main thread to the higher level cache and makes memory accesses indicated by the assist thread directly to the lower level cache without first accessing the higher level cache;
• and
• a scheduler that schedules execution of the assist thread and the main thread for simultaneous execution, wherein execution of the main thread is constrained such that each instruction in the main thread having a corresponding instruction in the assist thread always executes after the corresponding instruction in the assist thread.

A data processing system, comprising:

• a multi-level cache memory hierarchy including at least a higher level cache having a lower access latency and a lower level cache having a higher access latency;
• a main processor coupled to the multi-level memory hierarchy, wherein the main processor executes a main thread and makes memory accesses requested by instructions in the main thread to the higher level cache;
• an assist processor physically distinct from the main processor, wherein the assist processor executes an assist thread that is derived from a same source code object as the main thread and that contains a smaller subset of the instructions in the main thread, wherein the subset of instructions executed in the assist thread includes memory access instructions, those arithmetic instructions required to resolve memory references in the memory access instructions, and any branch instruction required to determine whether a memory access instruction among the memory access instructions is to be executed, and wherein the assist processor makes memory accesses requested by instructions in the assist thread directly to the lower level cache without first accessing the higher level cache;
• and
• a scheduler that schedules execution of the assist thread and the main thread for simultaneous execution, wherein execution of the main thread is constrained such that each instruction in the main thread having a corresponding instruction in the assist thread always executes after the corresponding instruction in the assist thread.