Transaction level model synthesis
AssigneeSynopsys, Inc.
InventorSerge Goossens
Life of this patent
Estimating the term…
Abstract
Converting from transaction level model to register transfer level. A method comprises accessing a transaction level model description. Function calls in the transaction level model description are automatically converted to signal accesses in a register transfer level description. Interface logic is automatically generated in the register transfer level description. The interface logic provides an interface between a bus interface and the signal accesses. The register transfer level description is stored in a computer readable medium.
Claims20
A computer implemented method comprising:
- receiving a transaction level model description of an integrated circuit;
- generating a synthesizable subset of the transaction level model description from the transaction level model description, the synthesizable subset including a communication portion and a behavioral portion, the communication portion independently synthesizable;
- automatically converting function calls in the synthesizable subset of the transaction level model description to signal accesses in a register transfer level description;
- automatically generating interface logic in the synthesizable subset of the register transfer level description, the interface logic comprising an interface between a bus interface and the signal accesses, the interface logic including combinational logic of a signal generator and buffer registers;
- and
- storing in a computer readable medium the register transfer level description including said signal accesses and the interface logic between the bus interface and said signal accesses.
A non-transitory computer readable medium comprising stored instructions to convert a transaction level model to a register transfer level that when executed causes or more processors to:
- receive a transaction level model description of an integrated circuit;
- generate a synthesizable subset of the transaction level model description from the transaction level model description, the synthesizable subset including a communication portion and a behavioral portion, the communication portion independently synthesizable;
- automatically convert function calls in the synthesizable subset of the transaction level model description to signal accesses in a register transfer level description;
- automatically generate interface logic in the synthesizable subset of the register transfer level description, the interface logic comprising an interface between a bus interface and the signal accesses, the interface logic including combinational logic of a signal generator and buffer registers;
- and
- store in the register transfer level description including said signal accesses and the interface logic between the bus interface and said signal accesses.
Dependencies are inferred from the claim text.