US 8,949,764 B2 · Excluding library cells for delay optimization in numerical synthesis

Abstract

Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively.

Claims18

Dependent claims

A method for determining a subset of a set of library cells of a library cell type for a timing arc of the library cell type, the method comprising:

receiving a first generic logical effort value for the timing arc of the library cell type, wherein the first generic logical effort value is determined by aggregating specific logical effort values across multiple library cells of the library cell type receiving a generic parasitic delay value for the timing arc of the library cell type;
and
determining, by using a computer, the subset of the set of library cells of the library cell type, wherein said determining comprises:
excluding library cells in the set of library cells of the library cell type whose specific logical effort values for the timing arc are greater than the first generic logical effort value by more than a first threshold, and
excluding library cells in the set of library cells of the library cell type whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold.

2 more elements

A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for determining a subset of a set of library cells of a library cell type for a timing arc of the library cell type, the method comprising:

receiving a first generic logical effort value for the timing arc of the library cell type, wherein the first generic logical effort value is determined by aggregating specific logical effort values across multiple library cells of the library cell type receiving a generic parasitic delay value for the timing arc of the library cell type;
and
determining the subset of the set of library cells of the library cell type, wherein said determining comprises:
excluding library cells in the set of library cells of the library cell type whose specific logical effort values for the timing arc are greater than the first generic logical effort value by more than a first threshold, and
excluding library cells in the set of library cells of the library cell type whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold.

2 more elements

A system, comprising:

a processor;
and
a storage medium storing instructions that, when executed by the processor, cause the system to perform a method for determining a subset of a set of library cells of a library cell type for a timing arc of the library cell type, the method comprising:
receiving a first generic logical effort value for the timing arc of the library cell type, wherein the first generic logical effort value is determined by aggregating specific logical effort values across multiple library cells of the library cell type receiving a generic parasitic delay value for the timing arc of the library cell type;
and
determining the subset of the set of library cells of the library cell type, wherein said determining comprises:
excluding library cells in the set of library cells of the library cell type whose specific logical effort values for the timing arc are greater than the first generic logical effort value by more than a first threshold, and
excluding library cells in the set of library cells of the library cell type whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold.

5 more elements

Dependencies are inferred from the claim text.

Excluding library cells for delay optimization in numerical synthesis

Life of this patent

Excluding library cells for delay optimization in numerical synthesis

Life of this patent

Abstract

Claims18