Computer-based modeling of integrated circuit congestion and wire distribution for products and services
AssigneeInternational Business Machines Corporation
InventorsCharles J. Alpert, Zhuo Li, Chin Ngai Sze, Jia Wang, Yaoguang Wei
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Abstract
A computer-based system and method for modeling integrated circuit congestion and wire distribution determines a boundary where a tile congestion corresponding to a first layer group is equivalent to a first blockage ratio corresponding to a second layer group, formulates a piece-wise linear formula that relates the tile congestion to a number of wires of a two-dimensional tile, and distributes a portion of the number of wires to a layer of the tile based on the tile congestion.
Claims10
A system for modeling circuit congestion, comprising:
- a boundary locator that determines a boundary where a tile congestion corresponding to a first layer group of a a two-dimensional tile is equivalent to a first blockage ratio corresponding to a second layer group of the two-dimensional tile;
- and
- a congestion estimator that formulates a segment of a piece-wise linear formula relating the tile congestion to a number of wires of the two-dimensional tile;
- wherein the tile congestion corresponding to the segment of the piece-wise linear formula is equal to a sum of the number of wires, the first blockage ratio and the second blockage ratio divided by a total capacity corresponding to the first and second layer groups.
A computer program product for modeling circuit congestion, the computer program product comprising a computer readable storage medium that is not a transitory signal per se, the computer readable storage medium having stored thereon:
- first program instructions executable by a processor to cause the processor to determine a boundary where a tile congestion corresponding to a first layer group of a two-dimensional tile is equivalent to a first blockage ratio corresponding to a second layer group of the two-dimensional tile;
- and
- second program instructions executable by the processor to cause the processor to formulate a segment of a piece-wise linear formula that relates the tile congestion to a number of wires of the two-dimensional tile;
- wherein the tile congestion corresponding to the segment of the piece-wise linear formula is equal to a sum of the number of wires, the first blockage ratio and the second blockage ratio divided by a total capacity corresponding to the first and second layer groups.
Dependencies are inferred from the claim text.