US 8,949,753 B1 · Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language

Abstract

Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.

Claims31

Dependent claims

A computer implemented method for implementing analog behavioral modeling and IP (intellectual property) integration using a Hardware Description Language, comprising:

at least one processor or at least one processor core executing a process, the process comprising:
identifying a first block that is represented using real signals in a digital modeling environment;
identifying a second block that is represented using logic signals in the digital modeling environment, wherein the second block is connected to the first block;
detecting a first connection in the first block that interacts with a second connection in the second block, wherein the second connection is incompatible with the first connection;
and
inserting a connect module between the first connection and the incompatible second connection.

3 more elements

An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a method for implementing analog behavioral modeling and IP (intellectual property) integration using a Hardware Description Language, the method comprising:

at least one processor or at least one processor core executing a process, the process comprising:
identifying a first block that is represented using real signals in a digital modeling environment;
identifying a second block that is represented using 4-state signals in the digital modeling environment, wherein the second block is connected to the first block;
detecting a first connection in the first block that interacts with a second connection in the second block, wherein the second connection is incompatible with the first connection;
and
inserting a connect module between the first connection and the incompatible second connection.

3 more elements

Dependencies are inferred from the claim text.

Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language

Life of this patent

Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language

Life of this patent

Abstract

Claims31