US 8,949,752 B2Granted

System and method of emulating multiple custom prototype boards

AssigneeSynopsys, Inc.

InventorsMing-Yang Wang, Sweyyan Shei

Life of this patent

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Abstract

An emulation system integrates multiple custom prototyping boards for emulating a circuit design. A first custom prototyping board including at least one FPGA and an interface connected to a first set of wires coupling to the at least one FPGA. A second custom prototyping board includes at least one second FPGA and an interface connected to a second set of wires coupling to the at least second FPGA. An adaptor board connects to the first custom prototyping board and the second custom prototyping board through the first interface and the second interface. The adapter board controls emulation of the circuit design and controls communication through the partitioned circuit using at least one of the first set of wires and at least one the second set of wires.

Claims20

Dependent claims

A method for emulating a circuit design using a plurality of prototyping boards, the method comprising:

connecting a first prototyping board having a set of programmable logic components to a first interface having a set of programmable logic components using a first set of wires, the first prototyping board being described by a first plurality of board description files;
partitioning the circuit design according to the first plurality of board description files into the first prototyping board using the set of programmable logic components of the first prototyping board for emulating the circuit design;
configuring the set of programmable logic components of the first prototyping board with a module configured to transmit data between the first prototyping board and the first interface using at least one of the first set of wires;
and
configuring the set of programmable logic components of the first interface with at least one of interface logic that provides communication with another interface or workstation connected to the first interface using a second set of wires or an interconnection fabric that provides communication between a plurality of prototyping boards.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/089,522Filed 25 Nov 2013 · us provisional application
Priority: 1 Dec 2012
Published: US 2014/0157215 A15 Jun 2014
Granted: 3 Feb 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 11/267
Functional testing: reconfiguring circuits for testing, e.g. LSSD, partitioning
G06F 30/331
Using simulation: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G06F
Computing and data processing