Circuit for forward error correction encoding of data blocks across multiple data lanes

A communication system, comprising:

• an FEC encoding circuit configured to receive a sequence of data bits and perform FEC encoding of the sequence of data bits to produce an FEC coded sequence formatted on a first set of N data lanes;
• an alignment marker circuit coupled to the FEC encoding circuit, the alignment marker circuit configured to periodically add alignment markers in the FEC coded sequence on each of N data lanes;
• a multiplexing circuit coupled to the alignment marker circuit, the multiplexing circuit configured to multiplex the N data lanes of the FEC coded sequence to produce a multiplexed sequence on a second set of M data lanes, M<N, the multiplexing of the data lanes being performed at boundaries between data symbols of the FEC coded sequence;
• and
• a driver circuit coupled to the multiplexing circuit and configured to transmit the multiplexed sequence over a data bus having M data lanes.

A receiver circuit, comprising:

• an alignment marker detection circuit configured to:
• receive a multiplexed data sequence from a data bus having a first set of M data lanes;
• and
• locate data symbol boundaries in the multiplexed data sequence;
• a demultiplexing circuit coupled to the alignment marker detection circuit, the demultiplexing circuit configured to demultiplex the multiplexed data sequence to produce an FEC coded sequence on a third set of N data lanes, the demultiplexing being performed at the located symbol boundaries in the multiplexed data sequence;
• and
• an FEC decoder circuit coupled to the demultiplexing circuit, the FEC decoder circuit configured to perform FEC decoding on the FEC coded sequence.