Method, apparatus and system for handling data faults
AssigneeIntel Corporation
InventorsZion S. Kwok, Scott Nelson
Life of this patent
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AssigneeIntel Corporation
InventorsZion S. Kwok, Scott Nelson
Estimating the term…
Techniques and mechanisms for handling data faults in a memory system which includes multiple integrated circuit (IC) dies, each die including a respective one of multiple memory arrays. In an embodiment, control logic monitors for a die failure of the multiple dies, and further monitors for a request to perform error correction for the multiple memory arrays. Each of the multiple memory arrays may store a respective vertical error correction code specific to data of that memory array. Another IC die may store a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code of a horizontal codeword which spans the multiple memory arrays. In another embodiment, the BCH code is available to decode logic for data recovery operations in response to a die failure, where the BCH code is further available to the decode logic for error correction operations when all of the memory arrays are operative.
A device comprising:
A system comprising:
A method comprising:
A non-transitory computer-readable storage medium having stored thereon instructions which, when executed by one or more processing units, cause the one or more processing units to perform a method comprising:
Dependencies are inferred from the claim text.