Address error detection
AssigneeInternational Business Machines Corporation
InventorRichard Nicholas
Life of this patent
Estimating the term…
Abstract
Address error detection including a method that receives write data and a write address, the write address corresponding to a location in a memory. Error correction code (ECC) bits are generated based on the received write data. The write data is transformed at a computer based on the write address and the write data, to produce transformed write data. The transforming is configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between either the write address or the read address and data read from the location. The transformed write data and the ECC bits are written to the location in memory.
Claims11
A method comprising:
- receiving write data and a write address, the write address corresponding to a location in a memory, the write address comprising a plurality of write address bits, and the write data comprising a plurality of write data bits grouped into write data blocks, each write address bit corresponding to a write data block;
- generating error correction code (ECC) bits based on the received write data;
- transforming, at a computer, the write data responsive to the write address and to the write data to produce transformed write data, the transforming configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between the write address and data read from the location, the transforming comprising:
- performing, for each of the write address bits, an exclusive-or (XOR) operation using the write address bit and its corresponding write data block as input, the XOR operation generating, based on a value of the write address bit, a transformed write data block that includes one of the received write data and a complement of the received write data;
- and
- combining the transformed write data blocks to create transformed write data;
- and
- writing the transformed write data and the ECC bits to the location in memory.
A system comprising:
- a memory;
- and
- a processor configured to perform a method, the method comprising:
- receiving write data and a write address, the write address corresponding to a location in a memory, the write address comprising a plurality of write address bits, and the write data comprising a plurality of write data bits grouped into write data blocks, each write address bit corresponding to a write data block;
- generating error correction code (ECC) bits based on the received write data;
- transforming the write data responsive to the write address and to the write data to produce transformed write data, the transforming configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between the write address and data read from the location, the transforming comprising:
- performing, for each of the write address bits an exclusive-or (XOR) operation using the write address bit and its corresponding write data block as input, the XOR operation generating, based on a value of the write address bit, a transformed write data block that includes one of the received write data and a complement of the received write data;
- and
- combining the transformed write data blocks to create transformed write data;
- and
- writing the transformed write data and the ECC bits to the location in memory.
Dependencies are inferred from the claim text.