Memory device and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsMan-keun Seo, Jun-jin Kong, Kyoung-Lae Cho
Life of this patent
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Abstract
A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit, and an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data, wherein each of the error correction blocks comprises the normal data, invalid data having a size corresponding to the size of the normal data, and parities for the normal data and the invalid data.
Claims20
An integrated circuit memory system, comprising:
- an error correction block generator comprising a data split circuit configured to divide a string of compressed data into a plurality of strings of normal data and an error correction encoding circuit configured to encode each of the plurality of strings of normal data into a respective error correction block,
- wherein each of the error correction blocks comprises combined data and an error correction code,
- wherein the combined data comprises normal data and invalid data, and
- wherein the error correction code is generated by encoding the combined data.
A memory system comprising:
- a data compressor for generating compressed data by compressing program data in a first unit;
- and
- an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data,
- wherein each of the error correction blocks comprises combined data and an error correction code,
- wherein the combined data comprises the normal data and invalid data, and
- wherein the error correction code signifies the parity of the combined data.
A memory device for storing a physical page including compressed data in which a plurality of logic pages are compressed, wherein the physical page comprises a plurality of error correction blocks,
- wherein each of the plurality of error correction blocks comprises combined data and an error correction code,
- wherein the combined data comprises normal data which comprises a part of the compressed data and invalid data having a size corresponding to a size of the normal data, and
- wherein the error correction code comprises a parity of the combined data.
Dependencies are inferred from the claim text.