Data receiver device and test method thereof

A digital display device comprising:

• a logic unit and a video system frequency control circuit configured to operate in either of a normal mode to execute digital video display processing and a test mode to execute a built-in self-test (BIST) process;
• an output terminal configured during the test mode to serialize a test pattern signal based on a test clock signal and to output an output signal;
• and
• an input terminal configured to serially receive an input signal, to recover a data signal and a data clock signal from the input signal based on the output signal, to deserialize the data signal based on the data clock signal, and during the test mode to output a test result signal to the logic unit, the test pattern signal and the test result signal are respective parallel signals,
• wherein, in the test mode, the logic unit is configured to generate the test pattern signal, receive the test result signal, and compare the test pattern signal with the test result signal to perform the BIST process, and
• wherein, in the test mode, the video system frequency control circuit is configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output the test clock signal.

A test method of a data receiver device, the test method comprising detecting whether a current operational mode of the data receiver device is a test mode or a normal mode, wherein upon detecting that the current operational mode is the test mode, the test method further comprising:

• generating a test pattern signal and a predetermined multiplication factor corresponding to the test pattern signal;
• generating a test clock signal by multiplying a reference clock signal by the multiplication factor;
• serializing the test pattern signal based on the test clock signal;
• outputting an output signal by driving the serialized test pattern signal;
• serially receiving an input signal;
• equalizing the input signal based on the test pattern signal;
• recovering a data signal and a data clock signal from the equalized input signal;
• generating a test result signal by deserializing the data signal based on the data clock signal;
• and
• performing a test by comparing the test result signal with the test pattern signal, the test pattern signal and the test result signal are respective parallel signals.