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US 8,949,648 B2Granted
System and method to overcome wander accumulation to achieve precision clock distribution over large networks
AssigneeSemtech Corporation
InventorMengkang Peng
Life of this patent
Estimating the term…
Abstract
A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard Precision Time Protocol (PTP) synchronization messages or similar time synchronization messages, each clock regenerator stage receives a grand clock error message from the previous stage, updates this error message with its own stage clock error, and then transmits the updated grand clock error to the next stage. This enables the synchronization algorithm to compensate for the error of the previous stage, effectively locking each clock regenerator stage to the grand master clock directly.
Claims19
A clock synchronization system for use in a network comprising a grand master clock, a first clock regenerator, and a second clock regenerator, wherein:
- the grand master clock includes a primary precision timing source;
- the first clock regenerator is operatively connected to the grand master clock, and to the second clock regenerator, wherein the first clock regenerator includes:
- a first local clock;
- and
- a first synchronization processing unit for synchronizing the first local clock to the grand master clock and configured to:
- receive a first master-to-slave message from the grand master clock;
- send a first slave-to-master message to the grand master clock;
- calculate a first master-to-slave path delay and a first slave-to-master path delay based at least in part on the first master-to-slave message and the first slave-to-master message;
- calculate a first stage clock error equal to one half of a difference between the first slave-to-master path delay and the first master-to-slave path delay;
- generate a first grand clock error equal to a sum of the first stage clock error and a grand clock baseline error, wherein the grand clock baseline error is set equal to zero;
- and
- synchronize the first local clock to the grand master clock based at least in part on the first stage clock error and the grand clock baseline error;
- transmit the first grand clock error to the second clock regenerator;
- and
- the second clock regenerator is operatively connected to the first clock regenerator, wherein the second clock regenerator includes:
- a second local clock;
- and
- a second synchronization processing unit for synchronizing the second local clock to the grand master clock and configured to:
- receive a second synchronization message from the first clock regenerator;
- receive a second delay response message from the first clock regenerator;
- receive and store the first grand clock error from the first clock regenerator;
- calculate a second master-to-slave path delay based at least in part on the second synchronization message;
- calculate a second slave-to-master path delay based at least in part on the second delay response message;
- calculate a second stage clock error equal to one half of a difference between the second slave-to-master path delay and the second master-to-slave path delay;
- calculate a second grand clock error equal to a sum of the first grand clock error and the second stage clock error;
- and
- synchronize the second local clock to the grand master clock based at least in part on the second stage clock error and the first grand clock error.
24 more elements
A clock synchronization system for use in a network having a grand master clock and N clock regenerators, where N is an integer greater than one, comprises:
- a first clock regenerator operatively connected to the grand master clock;
- a kth clock regenerator, wherein k is an integer between, but not including, 1 and N, comprising:
- an operative connection to a (k−1)th clock regenerator;
- an operative connection to a (k+1)th clock regenerator;
- a synchronization processing unit including:
- a kth processing element configured to:
- receive a master-to-slave message from the (k−1)th clock regenerator;
- send a slave-to-master message to the (k−1)th clock regenerator;
- calculate a kth master-to-slave path delay and a kth slave-to-master path delay based at least in part on the master-to-slave message and the slave-to-master message;
- calculate a kth stage clock error equal to one half of a difference between the kth slave-to-master path delay and the kth master-to-slave path delay;
- receive a (k−1)th grand clock error from the (k−1)th clock regenerator;
- calculate a kth grand clock error equal to a sum of the (k−1)th grand clock error and the kth stage clock error;
- synchronize the kth clock regenerator to the grand master clock based at least in part on the kth stage clock error and the (k−1)th grand clock error;
- and
- the (k+1)th clock regenerator using at least the kth grand clock error to synchronize the (k+1)th clock regenerator to the grand master clock;
- and
- an Nth clock regenerator operatively connected to an (N−1)th clock regenerator.
14 more elements
In a network comprising a grand master clock and N clock regenerators, where N is an integer greater than 1, a method of synchronizing each of the N clock regenerators to the grand master clock comprises the steps of:
- sending a master-to-slave message from the grand master clock to a first clock regenerator;
- sending a slave-to-master message from the first clock regenerator to the grand master clock;
- at the first clock regenerator, performing the steps of:
- calculating a first master-to-slave path delay and a first slave-to-master path delay based at least in part on the master-to-slave message and the slave-to-master message;
- calculating a first stage clock error equal to one half of a difference between the first slave-to-master path delay and the first master-to-slave path delay;
- generating a first grand clock error equal to a sum of the first stage clock error and a grand clock baseline error, wherein the grand clock baseline error is set equal to zero;
- and
- synchronizing the first clock regenerator to the grand master clock based at least in part on the first stage clock error and the grand clock baseline error;
- at a kth clock regenerator, wherein k is an integer greater than 1 and less than N, performing a synchronization process comprising the steps of:
- receiving a master-to-slave message from the (k−1)th clock regenerator;
- sending a slave-to-master message to the (k−1)th clock regenerator;
- receiving and storing a (k−1)th grand clock error from the (k−1)th clock regenerator;
- calculating a kth master-to-slave path delay and a kth slave-to-master path delay based at least in part on the master-to-slave message and the slave-to-master message;
- calculating a kth stage clock error equal to one half of a difference between the kth slave-to-master path delay and the kth master-to-slave path delay;
- calculating a kth grand clock error equal to a sum of the kth stage clock error and the (k−1)th grand clock error;
- and
- synchronizing the kth clock regenerator to the grand master clock based at least in part on the kth stage clock error and the (k−1)th grand clock error;
- and
- at the Nth clock regenerator, performing the steps of:
- receiving a master-to-slave message from the (N−1)th clock regenerator;
- sending a slave-to-master message to the (N−1)th clock regenerator;
- receiving and storing an (N−1)th grand clock error from the (N−1)th clock regenerator;
- calculating an Nth master-to-slave path delay and an Nth master-to-slave path delay based at least in part on the master-to-slave message and the slave-to-master message;
- calculating a Nth stage clock error equal to one half of a difference between the Nth slave-to-master path delay and the Nth master-to-slave path delay;
- and
- synchronizing the Nth clock regenerator to the grand master clock based at least in part on the Nth stage clock error and the (N−1)th grand clock error.
23 more elements
Dependencies are inferred from the claim text.