RISC processor apparatus and method for supporting X86 virtual machine

A method for processing data in a Reduced Instruction Set Computing (RISC) processor supporting an X86 virtual machine, comprising the following steps:

• Step A:
• setting a working mode of the RISC processor-based X86 virtual machine in the RISC processor;
• Step B:
• reading an instruction and distinguishing a virtual machine instruction set mode of the instruction, decoding the instruction according to the distinguished virtual machine instruction set mode of the instruction, and outputting the decoded instruction;
• and
• Step C:
• executing a corresponding computing or accessing processing according to the output decoded instruction, and outputting an execution result,
• wherein, when the X86 virtual machine supports a floating-point format and floating-point register stacks,
• the Step A includes:
• Step A1:
• setting a working mode of the RISC processor-based X86 virtual machine in the RISC processor, indicating that an emulation flag register is available;
• and
• Step A2:
• determining if floating-point registers are selected to emulate a floating-point register stack operation according to a stack enable bit, or setting a general register, of which the low 8 bits, from low to high, represent statuses of stack registers numbers 0-7 in the floating-point register stack, or selecting 3 general registers as a first floating-point register, a second floating-point register and a third floating-point register to perform a format conversion of a 64-bit floating-point number and a 80-bit floating-point number;
• the step B includes:
• Step B1:
• using a decoder to identify that an operation is in a working mode of emulating EFLAGS, and then decode the emulation flag register into a source register and/or a destination register according to different instructions;
• and
• Step B2:
• storing a value of the stack operation pointer in at least 3 bits of a top-of-stack (TOP) pointer register in the decoder, or decoding a newly added stack overflow determination instruction, or decoding an instruction for a conversion between an extended double-precision floating-point data and a double precision floating-point data;
• and
• the Step C includes:
• Step C1:
• when the RISC processor is in the working mode of the RISC processor-based X86 virtual machine during an operation process, reading and writing the values of flag bits in the emulation flag register to get and save operation status, and obtaining flag bits of the emulation flag register according to an operation result or executing a branch jump instruction according to one or more flag bits of the emulation flag register;
• and
• Step C2:
• when the floating-point register stack operation is emulated, operating a pointer register so as to emulate the stack operation of the stack operation pointer, and modify and monitor status of the stack operation pointer, or checking a specified stack register in the floating-point register stack and operating an overflow check register according to a value of the stack register so as to perform a floating-point stack overflow check, or executing a conversion between the extended double-precision floating-point data and the double-precision floating-point data.