Ineffective prefetch determination and latency optimization

A processor, comprising:

• an instruction source that provides an instruction stream for execution by the processor;
• an instruction fetcher, coupled to the instruction source, that fetches instructions from the instruction source;
• a prefetch cache, coupled to the instruction fetcher, that stores prefetched instructions, a particular instruction of the prefetched instructions being selected by the processor for ineffectiveness tracking to categorize the particular instruction into one of a plurality of prefetch effectiveness categories, wherein the processor tags the particular instruction as a target instruction;
• a plurality of execution units for executing instructions;
• a dispatcher, coupled to the instruction fetcher and the plurality of-execution units, that dispatches instructions to the plurality of execution units;
• and
• a performance monitoring unit (PMU), coupled to the instruction fetcher, the prefetch cache and the plurality of execution units, the PMU being configured to;
• initiate a timer to measure the time that the particular instruction ages in the prefetch cache before the particular instruction times out in the prefetch cache;
• and
• test for ineffectiveness of the prefetch of the particular instruction by accessing the timer to determine if timeout is reached for the particular instruction, thus designating an ineffective prefetched instruction;
• wherein the processor stores in a database prefetch information that includes a prefetch source address associated with the particular instruction, a prefetch age of the particular instruction and a category of prefetch effectiveness for the particular instruction;
• and
• wherein the processor PMU prohibits the processor from prefetching instructions from the instruction source in an address range associated with ineffective prefetched instructions.

An information handling system (IHS), comprising:

• a memory;
• and
• a processor coupled to the memory, the processor including:
• an instruction source that provides an instruction stream for execution by the processor;
• an instruction fetcher, coupled to the instruction source, that fetches instructions from the instruction source;
• a prefetch cache, coupled to the instruction fetcher, that stores prefetched instructions, a particular instruction of the prefetched instructions being selected by the processor for ineffectiveness tracking to categorize the particular instruction into one of a plurality of prefetch effectiveness categories, wherein the processor tags the particular instruction as a target instruction;
• a plurality of execution units for executing instructions;
• a dispatcher, coupled to the instruction fetcher and the plurality of execution units, that dispatches instructions to the plurality of execution units;
• and
• a performance monitoring unit (PMU), coupled to the instruction fetcher, the prefetch cache and the plurality of execution units, the PMU being configured to;
• initiate a timer to measure the time that the particular instruction ages in the prefetch cache before the particular instruction times out in the prefetch cache;
• and
• test for ineffectiveness of the prefetch of the particular instruction by accessing the timer to determine if timeout is reached for the particular instruction, thus designating an ineffective prefetched instruction;
• wherein the processor stores in a database prefetch information that includes a prefetch source address associated with the particular instruction, a prefetch age of the particular instruction and a category of prefetch effectiveness for the particular instruction;
• and
• wherein the processor PMU prohibits the processor from prefetching instructions from the instruction source in an address range associated with ineffective prefetched instructions.