Translation lookaside buffer structure including an output comparator

A method comprising:

• storing a respective physical address translation within at least one entry of a translation lookaside buffer including a data array having a plurality of entries;
• in response to a read access of a given entry, the data array outputting within a particular clock cycle, the respective translated physical address stored in the given entry;
• a plurality of differential sense amplifiers within the data array outputting inverted differential input bit representations of each bit of the translated physical address such that each bit of the translated physical address is precharged to an output logic value of zero during a portion of the particular clock cycle;
• comparing the respective translated physical address output by the data array with a plurality of additional addresses, during a remaining portion of the particular clock cycle;
• and
• providing a hit indication for each of the plurality of additional addresses within the particular clock cycle.

A translation lookaside buffer (TLB) comprising:

• a data array including a plurality of entries, wherein each entry is configured to store a respective translated physical address;
• wherein in response to a read access to a given entry, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry;
• wherein the data array includes a plurality of differential sense amplifiers configured to output inverted differential input bit representations of each bit of the translated physical address such that each bit of the translated physical address is precharged to an output logic value of zero during a portion of the particular clock cycle;
• and
• a compare unit coupled to the sense amplifier outputs of the data array and configured to concurrently compare, during a remaining portion of the particular clock cycle, the respective translated physical address output by the data array with a plurality of additional addresses, and to provide a hit indication for each of the plurality of additional addresses within the particular clock cycle.

A mobile communication device comprising:

• a memory;
• and
• a processor coupled to the memory, wherein the processor includes a translation lookaside buffer (TLB) unit including:
• a data array unit configured to output within a particular clock cycle, a translated physical address in response to a read request to a particular entry of the data array unit;
• wherein the data array unit includes a plurality of differential sense amplifiers configured to output inverted differential input bit representations of each bit of the translated physical address such that each bit of the translated physical address is precharged to an output logic value of zero during a portion of the particular clock cycle;
• and
• a compare unit coupled to the sense amplifier outputs of the data array unit and configured to concurrently compare, during a remaining portion of the particular clock cycle, the translated physical address with a plurality of additional addresses, and to provide a hit indication for each of the plurality of additional addresses within the particular clock cycle.