Effective address cache memory, processor and effective address caching method
AssigneeKabushiki Kaisha Toshiba
InventorsYasuhiko Kurosawa, Shigeaki Iwasa, Seiji Maeda, Nobuhiro Yoshida, Mitsuo Saito, Hiroo Hayashi
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Abstract
An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
Claims20
An effective address cache memory, comprising:
- a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process with a plurality of low-order bits including a least significant bit in the effective page tag as a first index, and output a hit signal when the effective page tag matches the effective page tag from a processor;
- a data memory configured to retain cache data corresponding to the same effective page tag as the TLB effective page memory for the same entry as the first index using a second index including the first index and a page offset;
- and
- a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the second index.
A processor comprising:
- a CPU;
- and
- a cache memory,
- wherein the cache memory comprises:
- a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process with a plurality of low-order bits including a least significant bit in the effective page tag as a first index, and output a hit signal when the effective page tag matches the effective page tag from a processor;
- a data memory configured to retain cache data corresponding to the same effective page tag as the TLB effective page memory for the same entry as the first index using a second index including the first index and a page offset;
- and
- a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the second index.
An effective address caching method, comprising:
- outputting a hit signal when an effective page tag in entry data in a TLB effective page memory matches the effective page tag from a processor, the TLB effective page memory being configured to retain the entry data including the effective page tag of predetermined high-order bits of an effective address of a process with a plurality of low-order bits including a least significant bit in the effective page tag as a first index;
- and
- when the hit signal is outputted, accessing a data memory configured to retain cache data corresponding to the same effective page tag as the TLB effective page memory for the same entry as the first index using a second index including the first index and a page offset, and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the second index.
Dependencies are inferred from the claim text.