Synchronizing a translation lookaside buffer with an extended paging table
AssigneeIntel Corporation
InventorsSteven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg
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Abstract
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
Claims11
A processor comprising:
- decode logic to decode an instruction providing a guest address of a virtualization based system, and an address space context corresponding to a page table of the virtualization based system;
- and
- execution logic, responsive to the decoded instruction, to invalidate a corresponding Translation Lookaside Buffer (TLB) entry with a mapping from the page table of the virtualization based system for the guest address.
A virtualization based system comprising:
- a memory to store an instruction specifying a context to identify a portion of an address space, and a guest address of the virtualization based system, the guest address to be mapped to a host address by a page table of the virtualization based system;
- and
- a processor to execute the instruction to cause an invalidation of one or more Translation Lookaside Buffer (TLB) entries with one or more corresponding mappings from the page table of the virtualization based system.
A machine implemented method comprising:
- mapping a guest address of a virtualization based system to a host address of the virtualization based system by a Translation Lookaside Buffer (TLB) entry from a page table of the virtualization based system;
- decoding an instruction specifying the guest address of the virtualization based system, and an address space context corresponding to said page table of the virtualization based system;
- and
- invalidating, responsive to the instruction, the corresponding TLB entry for the guest address of the virtualization based system.
Dependencies are inferred from the claim text.