Enhanced direct memory access

A system comprising:

• one or more processing cores, each core comprising one or more processors;
• memory for storing data and communicating the data to the one or more processors over a data communication interface;
• an application submitting a request to a data movement software to transfer data from a virtual source memory address to a virtual destination memory address,
• wherein the application is executed on a first core among a plurality of cores in a multi-core processor chip,
• wherein the first core is associated with a first on-chip cache exclusively dedicated to the first core, and
• wherein at least a second core from among said plurality of cores is associated with a second on-chip cache exclusively dedicated to the second core,
• wherein a first data movement thread associated with the data movement software is reserved by way of allocating a dedicated register file within the first on-chip cache, such that logic code for the first data movement thread fully resides within the first on-chip cache dedicated to the first core,
• wherein the data movement software, in response to determining that the application is executed on the first core, selects the first data movement thread to run on the first core to service the submitted request,
• wherein the first data movement thread shares the first on-chip cache with the application, while both the first data movement thread and the application are executed on the first core;
• wherein the first data movement thread directly loads the data requested by the application data to the first on-chip cache based on the virtual source memory address and the destination memory address information included in the request submitted by the application, instead of the first data movement thread copying the requested data first into a secondary on-chip cache sharable by the plurality of cores and then copying of the requested data from the secondary on-chip cache to the first on-chip cache;
• wherein a memory management unit (MMU) for the multi-core processor chip is provided with the virtual source memory address and the virtual destination memory address,
• wherein the MMU translates the virtual source memory address and the virtual destination memory address into a respective physical addresses for the source memory address and the destination memory address, without requiring a system call to pin down a memory region associated with the respective physical source memory address and the physical destination memory address,
• wherein the data movement software transfers the requested data from the physical source memory address to the physical destination memory address according to the MMU's translation, and
• wherein in response to determining that duplicate copies of the requested data are created in the first on-chip cache as the result of the transfer of the data, a cache line invalidation or a cache line flushing scheme is utilized to remove the duplicate copy.

A computer program product comprising a non-transitory computer usable medium including computer readable program code for facilitating direct memory access in a computing system in response to receiving a request to transfer data, wherein execution of the program code on a computer causes the computer to:

• submit a request to a data movement software to transfer data from a virtual source memory address to a virtual destination memory address, wherein an application is executed on a first core among a plurality of cores in a multi-core processor chip,
• wherein the first core is associated with a first on-chip cache exclusively dedicated to the first core,
• wherein at least a second core from among said plurality of cores is associated with a second on-chip cache exclusively dedicated to the second core,
• wherein a first data movement thread associated with the data movement software is reserved by way of allocating a dedicated register file within the first on-chip cache, such that logic code for the first data movement thread fully resides within the first on-chip cache dedicated to the first core,
• wherein the data movement software, in response to determining that the application is executed on the first core, selects the first data movement thread to run on the first core to service the submitted request,
• wherein the first data movement thread shares the first on-chip cache with the application while both the first data movement thread and the application are executed on the first core;
• wherein the first data movement thread directly loads the data requested by the application to the first on-chip cache based on the virtual source memory address and the destination memory address information included in the request submitted by the application, instead of the first data movement thread copying the requested data first into a secondary on-chip cache sharable by the plurality of cores and then copying of the requested data from the secondary on-chip cache to the first on-chip cache,
• wherein a memory management unit (MMU) for the multi-core processor chip is provided with:
• the virtual source memory address and the virtual destination memory address,
• wherein the MMU translates the virtual source memory address and the virtual destination memory address into respective physical source memory address and physical destination memory address, without requiring a system call to pin down a memory region associated with the respective physical source memory address and the physical destination memory address,
• wherein the data movement software transfers the requested data from the physical source memory address to the physical destination memory address according to the MMU's translation, and
• wherein in response to determining that duplicate copies of the requested data are created in the first on-chip cache as the result of the transfer of the data, a cache line invalidation or a cache line flushing scheme is utilized to remove the duplicate copy.