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US 8,949,567 B2Granted
Cross-point resistive-based memory architecture
AssigneeSeagate Technology LLC
InventorsAntoine Khoueir, Jon D. Trantham, Kevin Gomez, Ara Patapoutian
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Abstract
A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells. A controller is configured to couple to the array and to a host system. The controller is configured to perform receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size, and storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.
Claims20
An apparatus, comprising:
- a plurality of addressable memory tiles each comprising one or more cross-point arrays, each array comprising a plurality of non-volatile resistance-change memory cells;
- and
- a controller configured to couple to the array and to a host system, the controller configured to perform:
- receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size;
- and
- storing the one or more data objects in a corresponding integer number of one or more of the memory tiles.
3 more elements
An apparatus, comprising:
- a cross-point memory array comprising:
- a plurality of word lines;
- a plurality of bit lines intersecting the plurality of word lines at a plurality of cross-points;
- a resistance-change memory cell provided at each of the cross-points, each of the memory cells having an area of 4F2, where F denotes a minimum working dimension, and the resistance-change memory cells defining a plurality of addressable memory tiles;
- and
- a controller configured to couple to the cross-point array and to a host system, the controller configured to perform:
- receiving, from the host system, one or more data objects each having a size equal to a predetermined logical block size;
- and
- storing the one or more data objects in a corresponding integer number of one or more memory tiles of the array.
6 more elements
A method, comprising:
- receiving one or more data objects each having a size equal to a predetermined logical block size;
- and
- storing the one or more data objects in a corresponding integer number of one or more addressable memory tiles each comprising one or more cross-point arrays, each array comprising a plurality of cross points and each cross point comprising a non-volatile resistance-change memory cell and devoid of a select component.
Dependencies are inferred from the claim text.