Methods for sustained read and write performance with non-volatile memory
AssigneeVirident Systems Inc.
InventorsVijay Karamcheti, Shibabrata Mondal, Ajith Kumar
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AssigneeVirident Systems Inc.
InventorsVijay Karamcheti, Shibabrata Mondal, Ajith Kumar
Estimating the term…
In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.
A method of matching a memory capacity utilization rate to a memory capacity reclamation rate for a non-volatile memory system, the method comprising:
A method for a non-volatile memory system, the method comprising:
A method for garbage collection in a non-volatile memory system, the method comprising:
Dependencies are inferred from the claim text.