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US 8,949,554 B2Granted
Idle power control in multi-display systems
AssigneeAdvanced Micro Devices, Inc.
InventorsGreg Sadowski, Stephen Presant
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorsGreg Sadowski, Stephen Presant
Estimating the term…
A system and method for reducing power consumption of a video subsystem. A computer system includes multiple display devices supported by a graphics processor. A memory for storing video data for the multiple display devices utilizes multiple channels for higher bandwidth. A systems controller within the graphics processor determines a retraining condition, such as an idle power state, is satisfied for one or more channels of the multiple memory channels. The graphics processor divides each respective screen for the multiple display devices into multiple horizontal bars. For each one of the multiple horizontal bars, the corresponding data may be rearranged from being distributed across the multiple channels to being stored in a single one of the multiple channels. The systems controller determines a given channel is an upcoming free channel. This free channel is retrained while it is free. Retraining may include at least reducing its memory clock (MCLK) frequency.
A processor comprising:
A method for use in a system configured to generate data for a display device, the method comprising:
A computer system comprising:
Dependencies are inferred from the claim text.
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Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen: arrangements specially adapted for…
Power saving in peripheral device: power saving in display device
Controlling a plurality of local displays, e.g. CRT and flat panel display: using a single graphics controller
Characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory: graphics controllers
About 6 years 6 months of term left · ends 30 Apr 2033 (estimated)
1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to reducing power consumption of a video subsystem.
2. Description of the Relevant Art
FIG. 1 is a generalized block diagram of one embodiment of a video subsystem.
FIG. 2 is a generalized block diagram of one embodiment of video data storage arrangement.
FIG. 3 is a generalized block diagram of another embodiment of video data storage arrangement.
While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention might be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention.
Turning to FIG. 1, a generalized block diagram of one embodiment of a video subsystem 100 is shown. As shown, multiple display devices 102a-102g are connected to a graphics processor 110. As used herein, a graphics processor may also be referred to as a graphics processing unit (GPU) or processing unit. One or more memory channels 104a-104h may also be connected to the graphics processor 110. Each of the memory channels 104a-104h may be a separate interface to a memory, such as a dynamic random access memory (DRAM). As used herein, a memory channel may also be referred to as a channel.