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US 8,949,551 B2Granted
Memory protection unit (MPU) having a shared portion and method of operation
AssigneeFreescale Semiconductor, Inc.
InventorWilliam C. Moyer
Life of this patent
Estimating the term…
Abstract
In a disclosed embodiment, a data processing system comprises a memory protection unit (MPU); and a plurality of region descriptors associated with the MPU. Each region descriptor is associated with one of multiple subsets of the region descriptors and includes an address range, protection settings, and attributes for a respective region of memory. The subsets include data-only region descriptors, instruction-only region descriptors, and shared region descriptors. The shared region descriptors are used to access memory regions for data and instruction memory requests.
Claims20
A data processing system comprising:
- a memory protection unit (MPU);
- a plurality of region descriptors associated with the MPU, wherein each region descriptor is associated with one of multiple subsets of the region descriptors and includes an address range, protection settings, and attributes for a respective region of memory, the subsets including a subset of data-only region descriptors, a subset of instruction-only region descriptors, and a subset of shared region descriptors;
- a first shared region descriptor of the subset of shared region descriptors, the first shared region descriptor including a first indicator to selectively configure the first shared region descriptor to operate as one of a data region descriptor or an instruction region descriptor;
- first instruction compare logic coupled to an instruction address bus and to the first shared region descriptor, the first instruction compare logic to compare an address at the instruction address bus with a first address range specified at the first region descriptor;
- and
- first data compare logic coupled to a data address bus and to the first shared region descriptor, the first data compare logic to compare an address at the data address bus with the first address range;
- wherein the first instruction compare logic is enabled and the first data compare logic is disabled if the first indicator is in a first state;
- and
- wherein the first instruction compare logic is disabled and the first data compare logic is enabled if the first indicator is in a second state.
6 more elements
A data processing system comprising:
- a memory protect unit (MPU) including:
- a set of instruction region descriptors to selectively allow or deny instruction access requests;
- first instruction compare logic to control access to a memory for the instruction access requests;
- a set of data region descriptors to selectively allow or deny data access requests;
- first data compare logic to control access to the memory for the data access requests;
- a set of shared region descriptors, wherein each shared region descriptor is selectively configurable to operate as one of a data region descriptor or an instruction region descriptor, the set of shared region descriptors including a first shared region descriptor, the first shared region descriptor including a first indicator to selectively configure the first shared region descriptor to operate as one of a data region descriptor or an instruction region descriptor;
- second instruction compare logic coupled to an instruction address bus and to the first shared region descriptor, the first instruction compare logic to compare an address at the instruction address bus with a first address range specified at the first region descriptor;
- and
- second data compare logic coupled to a data address bus and to the first shared region descriptor, the first data compare logic to compare an address at the data address bus with the first address range;
- wherein the second instruction compare logic is enabled and the second data compare logic is disabled if the first indicator is in a first state;
- and
- wherein the second instruction compare logic is disabled and the second data compare logic is enabled if the first indicator is in a second state.
9 more elements
A method comprising:
- determining whether a shared indicator included at an assist register of a memory protection unit (MPU) is in a first state, the assist register for updating region descriptors of the MPU;
- if the shared indicator is in the first state, selecting an entry in a set of shared region descriptors in the MPU of a data processing system for access, wherein a shared region descriptor is selectively configurable to operate as one of a data region descriptor or an instruction region descriptor based on an indicator included at the region descriptor;
- determining whether the shared indicator is in a second state;
- and
- if the shared indicator is in the second state, selecting an entry in a set of data region descriptors or a set of instruction region descriptors in the MPU for access, and disabling selection of an entry in the set of shared region descriptors for access.
2 more elements
Dependencies are inferred from the claim text.