Memory interface device and methods thereof
AssigneeFreescale Semiconductor, Inc.
InventorJohn D. Pape
Life of this patent
Estimating the term…
Abstract
A data processing device includes a load/store module to provide an interface between a processor device and a bus. In response to receiving a load or store instruction from the processor device, the load/store module determines a predicted coherency state of a cache line associated with the load or store instruction. Based on the predicted coherency state, the load/store module selects a bus transaction and communicates it to the bus. By selecting the bus transaction based on the predicted cache state, the load/store module does not have to wait for all pending bus transactions to be serviced, providing for greater predictability as to when bus transactions will be communicated to the bus, and allowing the bus behavior to be more easily simulated.
Claims20
A method comprising:
- receiving a first memory request associated with a first address;
- in response to receiving the first memory request, determining, via a control module within a load/store module, a first predicted coherency state of a first cache location associated with the first address by selecting the first predicted coherency state from a plurality of possible states based on a type of a first pending bus transaction associated with the first address, the first pending bus transaction resulting from a second memory request received prior to the first memory request, the type of the first pending bus transaction selected from the group consisting of a load transaction and a store transaction;
- determining, via the control module, a first bus transaction based on the first predicted coherency state;
- and
- communicating the first bus transaction.
A method, comprising:
- receiving a first stimulus indicative of a first simulated memory request associated with a first address;
- determining, via a control module within a load/store module, a first predicted coherency state of a first simulated cache location associated with the first address based on a type of a first pending bus transaction associated with the first address, the first pending bus transaction resulting from a second simulated memory request received prior to the first stimulus, the type of the first pending bus transaction selected from the group consisting of a load transaction and a store transaction;
- determining, via the control module, a first bus transaction based on the first predicted coherency state;
- and
- simulating operation of a bus based on the first bus transaction.
A device, comprising:
- a cache;
- a load/store module further comprising:
- a pending bus transaction queue comprising an input configured to receive bus transactions and an output coupled to a bus, the pending bus transaction queue configured to store pending bus transactions associated with the cache;
- and
- a control module comprising an input configured to receive a first memory request associated with the cache, an input coupled to the cache and an output coupled to the input of the pending bus transaction queue, the output configured to communicate bus transactions in response to the memory requests, the control module configured to select one or more of the bus transactions based on a predicted coherency state of a cache line of the cache, the predicted coherency state based on types of pending bus transactions stored at the pending bus transaction queue prior to receiving the first memory request, the types of pending bus transactions selected from the group consisting of load transactions and store transactions.
Dependencies are inferred from the claim text.