Lateral castout (LCO) of victim cache line in data-invalid state

A data processing system, comprising:

• an interconnect fabric;
• and
• a plurality of processing units coupled to the interconnect fabric, the plurality of processing units including a first processing unit and a second processing unit, wherein the first processing unit has a first processor core and associated first upper and first lower level caches, and wherein the second processing unit has a second processor core and associated second upper and lower level caches;
• wherein the first lower level cache includes:
• a data array including a plurality of congruence classes including a congruence class containing a plurality of cache lines, and
• a directory of the data array;
• wherein the first processing unit, responsive to a need to evict one of the plurality of cache lines, selects a victim cache line to be evicted from the congruence class of the first lower level cache and determines, based at least on a coherence state of the victim cache line, whether to perform a lateral castout (LCO) to a lower level cache of another of the plurality of processing units or a castout to a system memory, wherein the first processing unit determines to perform a LCO of a coherence state of the victim cache line responsive to the victim cache line having a first data-invalid coherence state and determines to perform a castout of the coherence state of the victim cache line to the system memory responsive to the victim cache line having a second data-invalid coherence state;
• wherein the first processing unit, responsive to determining to perform the LCO of the coherence state of the victim cache line, issues a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies an address of the victim cache line to be evacuated from the first lower level cache, indicates the first data-invalid coherence state, and indicates that a lower level cache is an intended destination of the coherence state of the victim cache line;
• and
• wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit evacuates the victim cache line from the first lower level cache and a directory of the second lower level cache associates the address of the victim cache line with the first data-invalid coherence state, wherein the LCO command does not transfer data of the victim cache line from the first lower level cache to the second lower level cache.

A processing unit for a data processing system including a plurality of processing units coupled by an interconnect fabric, the processing unit comprising:

• a first processor core and associated first upper and first lower level caches, wherein the first lower level cache includes:
• a data array including a plurality of congruence classes including a congruence class containing a plurality of cache lines, and
• a directory of the data array;
• wherein the processing unit, responsive to a need to evict one of the plurality of cache lines, selects a victim cache line to be evicted from the congruence class of the first lower level cache and determines, based at least on a coherence state of the victim cache line, whether to perform a lateral castout (LCO) to a lower level cache of another of the plurality of processing units or a castout to a system memory, wherein the first processing unit determines to perform a LCO of a coherence state of the victim cache line responsive to the victim cache line having a first data-invalid coherence state and determines to perform a castout of the coherence state of the victim cache line to the system memory responsive to the victim cache line having a second data-invalid coherence state;
• wherein the processing unit, responsive to determining to perform the LCO of the coherence state of the victim cache line, issues a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies an address of the victim cache line to be evacuated from the first lower level cache, indicates the first data-invalid coherence state, and indicates that a lower level cache is an intended destination of the coherence state of the victim cache line;
• and
• wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the processing unit evacuates the victim cache line from the first lower level cache for association by a directory of a second lower level cache with the first data-invalid coherence state, wherein the LCO command does not transfer data of the victim cache line from the first lower level cache to the second lower level cache.