Conditional load and store in a shared memory

A system for implementing conditional memory reservations in a multi-processor computing system to maintain memory consistency in a shared memory, the computing system including a multitude of processor units and a shared memory, wherein all of the processor units have access to the shared memory, and the processor units make load-reserve requests to reserve an address in the shared memory and make store-conditional requests to store data to the reserved address in the shared memory, the system for implementing conditional memory reservations comprising:

• a series of reservation registers included in the shared memory to support load- reserve/store conditional locks, and for storing addresses in the shared memory reserved for each of the processor units of the computing system to store data, each of the reservation registers including an address field and a valid bit;
• and
• one or more of the processor units of the computing system configured for:
• using the shared memory to maintain consistency in the shared memory, including:
• in response to one of the processor units making a conditional load-reserve request, storing in one of said reservation registers an address in the shared memory to lock said address for said one of the processor units to maintain consistency of data in the shared memory, and setting the valid bit in the one of the registers to indicate that the address stored in said one of the registers is reserved for said one of the processor units, wherein in response to defined events, the valid bit in said one of the registers is reset to indicate that the address stored in said one of the registers is not reserved for said one of the processor units, including when one of the other processor units stores data at said address in the shared memory, the valid bit in said one of the registers is invalidated to indicate that the address stored in said one of the registers is not reserved for said one of the processor units;
• in response to said one of the processor units making a store-conditional store request to store data at said address in the shared memory, checking the valid bit in said one of the reservation registers to determine if said address in the shared memory is reserved for said one of the processor units;
• and
• if the valid bit in said one of the reservation registers shows that said address in the shared memory is not reserved for said one of the processor units, not storing the data of said store-conditional request at said address in the shared memory.
• if the reservation registers shows that an address is validly reserved for said one of the processors, storing the data of said store-conditional request at said address in the shared memory.

A system for implementing conditional memory reservations in a multi-processor computing system to maintain memory consistency in a shared memory, the computing system including a multitude of processor units and a shared memory, wherein all of the processor units have access to the shared memory, and the processor units make load-reserve requests to reserve an address in the shared memory and make store-conditional requests to store data to the reserved address in the shared memory, the system for implementing conditional memory reservations comprising:

• a series of reservation registers included in the shared memory to support load-reserve/store conditional locks, and for storing addresses in the shared memory reserved for each of the processor units of the computing system to store data, each of the reservation registers including an address field and a valid bit;
• and
• one or more of the processor units of the computing system configured for:
• using the shared memory to maintain consistency in the shared memory, including:
• in response to one of the processor units making a conditional load-reserve request, storing in one of said reservation registers an address in the shared memory to lock said address for said one of the processor units to maintain consistency of data in the shared memory, and setting the valid bit in the one of the registers to indicate that the address stored in said one of the registers is reserved for said one of the processor units, wherein in response to defined events, the valid bit in said one of the registers is reset to indicate that the address stored in said one of the registers is not reserved for said one of the processor units, including when one of the other processor units stores data at said address in the shared memory, the valid bit in said one of the registers is invalidated to indicate that the address stored in said one of the registers is not reserved for said one of the processor units;
• in response to said one of the processor units making a store-conditional request to store data at said address in the shared memory, checking the valid bit in said one of the reservation registers to determine if said address in the shared memory is reserved for said one of the processor units;
• and
• if the valid bit in said one of the reservation registers shows that said address in the shared memory is not reserved for said one of the processor units, not storing the data of said store-conditional request at said address in the shared memory;
• if the reservation registers shows that an address is validly reserved for said one of the processors, storing the data of said store-conditional request at said address in the shared memory.

An article of manufacture comprising:

• at least one tangible computer readable device having computer readable program code logic tangibly embodied therein to execute machine instructions in one or more processing units for implementing load and store instructions in a multi-processor computing system to maintain memory consistency in a shared memory, the computing system including a multitude of processor units, a shared memory, and a series of reservation registers included in the shared memory to support load-reserve/store conditional locks, each of the reservation registers including an address field and a valid bit, wherein all of the processor units have access to the shared memory and the processor units make load-reserve requests to reserve an address in the shared memory and make store-conditional requests to store data to the reserved address in the shared memory, said computer readable program code logic, when executing, performing the following:
• using the shared memory to maintain consistency in the shared memory, including:
• when one of the processor units makes a load-reserve request, storing in one of said reservation registers an address in the shared memory to lock said address for said one of the processor units to maintain consistency of data in the shared memory, and setting the valid bit in the one of the registers to indicate that the address stored in said one of the registers is reserved for said one of the processor units, wherein in response to defined events, the valid bit in said one of the registers is reset to indicate that the address stored in said one of the registers is not reserved for said one of the processor units, including when one of the other processor units stores data at said address, wherein in response to defined events, the valid bit in said one of the registers is reset to indicate that the address stored in said one of the registers is not reserved for said one of the processor units, including, the valid bit in said one of the registers is invalidated to indicate that the address stored in said one of the registers is not reserved for said one of the processor units;
• when said one of the processor units makes a store-conditional request to store data at said address in the shared memory, checking the valid bit in said one of the reservation registers to determine if said address in the shared memory is reserved for said one of the processor units;
• if the valid bit in said one of the reservation registers shows that said address in the shared memory is reserved for said one of the processor units, storing the data of said store-conditional request at said address in the shared memory;
• and
• if the valid bit in said one of the reservation registers shows that said address in the shared memory is not reserved for said one of the processor units, not storing the data of said store-conditional request at said address in the shared memory.

A method of implementing load-reserve and store-conditional instructions in a multi-processor computing system to maintain memory consistency in a shared memory, the computing system including a multitude of processor units, a multitude of L1 memory caches, and an L2 shared memory cache, and the processor units make load-reserve requests to reserve an address in the L2 shared memory and make store-conditional requests to store data to the reserved address in the shared memory, wherein each of the processor units has access to one of the L1 memory caches, and all of the processor units have access to the L2 shared memory cache, the method comprising:

• including in the L2 memory cache a series of reservation registers to support load-reserve/store conditional locks, each of the reservation registers including an address field and a valid bit;
• using the L2 shared memory to maintain consistency in the L2 shared memory, including:
• in response to one of the processor units making a load-reserve request, storing in one of said reservation registers an address in the shared memory to lock said address for said one of the processor units to maintain consistency of data in the shared memory, and setting the valid bit in the one of the registers to indicate that the address stored in said one of the registers is reserved for said one of the processor units, wherein in response to defined events, the valid bit in said one of the registers is reset to indicate that the address stored in said one of the registers is not reserved for said one of the processor units, including when one of the other processor units stores data at said address in the shared memory, the valid bit in said one of the registers is invalidated to indicate that the address stored in said one of the registers is not reserved for said one of the processor units;
• in response to said one of the processor units making a store-conditional request to store data at said address in the L2 shared memory, checking the valid bit in said one of the reservation registers to determine if said address in the shared memory is reserved for said one of the processor units;
• if the valid bit in said one of the reservation registers shows that said address is reserved for said one of the processor units, storing the data of said store-conditional request at said address in the L2 shared memory;
• and if the valid bit in said one of the reservation registers shows that said address in the shared memory is not reserved for said one of the processor units, not storing the data of said store-conditional request at said address in the shared memory.