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US 8,949,538 B2Granted
Interface device accessing a stack of memory dice and a solid state disk
AssigneeMicron Technology, Inc.
InventorJoe M. Jeddeloh
Life of this patent
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Abstract
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.
Claims22
An interface device comprising:
- a control circuit to control first exchanged information between a first bus and a second bus;
- a first sequencer to control second exchanged information between the second bus and the interface device;
- a second sequencer to control third exchanged information between memory channels and the interface device, wherein the interface device is coupled to a plurality of memory dice over the memory channels;
- and
- a cache control circuit to control fourth exchanged information between the first bus and the memory channels,
- wherein the control circuit is configured to control the interface device to determine if the first, second, and/or third exchanged information is located in the plurality of memory dice and/or a solid state disk and to select which of the plurality of memory dice or the solid state disk has a shortest latency to obtain the first, second, and/or third exchanged information.
3 more elements
An interface device comprising:
- a control circuit to couple data between a processor, separate from the interface device, and a solid state disk, separate from the interface device;
- a first sequencer to couple data between the interface device and the solid state disk, the first sequencer coupled to a first write buffer and a first read buffer;
- a second sequencer to couple data between the interface device and a plurality of memory dice, the second sequencer coupled to a second write buffer and a second read buffer;
- and
- a cache control circuit to couple data between the processor and the plurality of memory dice,
- wherein the control circuit is configured to control the interface device to determine if requested data is located in the plurality of memory dice and/or the solid state disk and to select which of the plurality of memory dice or the solid state disk has a shortest latency to obtain the requested data.
3 more elements
A system comprising:
- a stack of dice comprising a plurality of memory dice and an interface device, the interface device comprising:
- a control circuit to couple data between a processor and a solid state disk, both being separate from the stack;
- a first sequencer to couple data between the stack of dice and the solid state disk;
- a second sequencer to couple data between the interface device and the plurality of memory dice;
- and
- a cache control circuit to couple data between the processor and the stack of dice,
- wherein the control circuit is configured to control the interface device to determine if requested data is located in the stack of dice and/or the solid state disk and to select which of the stack of dice or the solid state disk has a shortest latency to obtain the requested data.
4 more elements
Dependencies are inferred from the claim text.