Multi-CPU system and computing system having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHoi Jin Lee, Young Min Shin
Life of this patent
Estimating the term…
Abstract
A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.
Claims38
A multi-CPU data processing system, comprising:
- a multi-CPU processor, comprising:
- a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache;
- and
- a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.
A multi-CPU data processing system, comprising:
- a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access data from the first cache;
- and
- a second CPU configured with at least a second core, and a second cache controller configured to access data from a second cache, wherein the first cache is configured from a shared portion of the second cache,
- wherein the first CPU excluding the first cache is embodied in a first die and the second CPU is embodied in a second die.
A method of data processing using a multi-CPU processor, comprising:
- accessing a first cache by a first CPU via a first cache controller;
- accessing a second cache by a second CPU via a second cache controller, wherein the first cache is configured from a shared portion of the second cache;
- and
- switching cache access operation from the first CPU to the second CPU without flushing of the first cache.
A processor, comprising:
- a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache;
- a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, the second cache is larger in storage capacity than the first cache;
- a multiplexer configured to pass data to the first cache from either the first core via the first cache controller or the second core via the second cache controller based on a selection signal;
- and
- a demultiplexer configured to pass data from the first cache to either the first core via the first cache controller or the second core via the second cache controller based on the selection signal.
A multi-CPU data processing system, comprising:
- a multi-CPU processor, comprising:
- a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache;
- a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache;
- a power management unit configured to selectively supply power to either or both of the first CPU and the second CPU and the first cache;
- and
- a memory controller configured to control memory access to and from the multi-CPU processor via a databus.
Dependencies are inferred from the claim text.