Performance of a stride-based prefetcher on an out-of-order processing unit (CPU)

A method, comprising:

• executing, with a processor in an out-of-order central processing unit (CPU), program code (PC) comprising a current instruction;
• generating a load virtual address (VA) access stride, with an out-of-order stride prefetch unit coupled to the processor, using an offset between a past VA access and a current VA access, wherein the current VA access is retrieved from the current instruction;
• and
• determining a smallest estimate VA access stride, with the out-of-order stride prefetch unit, based on a comparison between the load VA access stride and a past VA access stride.

A method for improving performance of a stride-based prefetcher on an out-of-order central processing unit (CPU), the method comprising:

• a.) loading a virtual address (Ld VA) from a CPU program code (PC) instruction;
• b.) determining whether there is an entry for the PC in a Stride Queue (StrideQ) table;
• c.) if there is no entry for the PC in the StrideQ table, creating an initialization StrideQ table entry for the PC, and repeating steps a.) and b.);
• d.) if there is an entry for the PC in the StrideQ table, computing a load stride (Ld Stride);
• e.) applying a matching algorithm using the Ld Stride and a read stride (Rd Stride);
• f.) updating the StrideQ table according to the matching algorithm results;
• g.) determining whether a State field in the StrideQ table is set to steady;
• h.) if the State field in the StrideQ table is not set to steady, repeating steps a.), b.), c.), d.), e.), f.), and g.) until the State field in the StrideQ table is set to steady;
• and
• i.) if the State field in the StrideQ table is set to steady, issuing a prefetch for a calculated virtual address (VA).