Maintenance operations in a DRAM

A memory controller to control a dynamic memory device that includes a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:

• refresh logic to generate an auto-refresh command for transmission to the memory device, wherein responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh memory cells and the command interface is placed into a calibration mode for at least a portion of the first time interval;
• and
• calibration logic to concurrently, during at least a portion of the first time interval while the memory device is performing refresh operations, perform a calibration of the command interface of the memory device;
• wherein responsive to the auto-refresh command, the command interface is placed into a loopback mode for at least the portion of the first time interval.

A dynamic memory device comprising:

• a plurality of memory banks, each bank including a plurality of rows of memory cells;
• a command interface operable to accept commands from a memory controller;
• refresh circuitry configured to refresh memory cells for a duration of a first time interval in response to an auto-refresh command from the memory controller;
• and
• control logic, in response to the auto-refresh command, to configure the command interface to, for at least a portion of the duration of the first time interval, not accept commands from the memory controller and to instead enter a calibration mode, wherein in the calibration mode, the command interface does not accept commands from the memory controller and is configured for calibration operations initiated by the memory controller;
• wherein the control logic, in response to the auto-refresh command, is to configure the command interface to enter a loopback mode, wherein in the loopback mode, the command interface receives a pattern on a first data path, and transmits the data pattern to the memory controller on a second data path.

A method of operating a memory device in a system that includes the memory device and a memory controller, the memory device including a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells, the method comprising:

• receiving an auto-refresh command from the memory controller at the memory device;
• responsive to the auto-refresh command, during a first time interval, refreshing memory cells in the memory device;
• and
• responsive to the auto-refresh command, placing the command interface from a normal operation mode into a calibration and loopback mode for at least a portion of the duration of the first time interval,
• wherein, in the calibration and loopback mode, the command interface receives a pattern on a first data path, and transmits the data pattern to the memory controller on a second data path,
• wherein the command interface accepts commands from the controller in the normal operation mode, and
• wherein the command interface does not accept commands from the controller in the calibration and loopback mode, and is instead configured for calibration operations initiated by the memory controller.

A dynamic memory device comprising:

• a plurality of memory banks, each bank including a plurality of rows of memory cells;
• a command interface to receive a single auto-refresh command, the single auto-refresh command specifying a bank order, the specified bank order comprising a specified sequence of the plurality of memory banks determined by the memory controller;
• at least one row refresh register to store a value that identifies a respective row of the plurality of rows of memory cells in each bank;
• and
• control circuitry coupled to the command interface, the row refresh register and the plurality of memory banks, the control circuitry being configured to sequentially refresh the respective row in the plurality of memory banks, in the specified bank order, wherein the specified bank order specifies a respective memory bank, of the plurality of memory banks, that is to be refreshed first in response to the received refresh command.