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US 8,949,514 B2Granted
Stack processor using a ferroelectric random access memory (F-RAM) for both code and data space
AssigneeCypress Semiconductor Corporation
InventorFranck Fillere
Life of this patent
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Abstract
A stack processor using a ferroelectric random access memory (F-RAM) for both code and data space which presents the advantages of easy stack pointer management inasmuch as the stack pointer is itself a memory address. Further, the time for saving all critical registers to memory is also minimized in that all registers are already maintained in non-volatile F-RAM per se.
Claims16
An integrated circuit device comprising:
- a stack processor comprising a processor core and an interrupt controller;
- and
- a ferroelectric random access memory coupled to said processor core for storing associated program code and data,
- wherein the stack processor further comprises a data stack including a top portion comprising first volatile memory in the processor core and a bottom portion comprising a first portion of the ferroelectric random access memory, and a return stack including a top portion comprising second volatile memory in the processor core and a bottom portion comprising a second portion of the ferroelectric random access memory, wherein the stack processor is configured to transfer data between the data and return stacks in response to a stack-based computer programming language comprising 64 possible instructions based upon a 16 bit word, and wherein each of said instructions in said 16 bit word comprises 3 five bit instructions and a 16th bit applicable to each of said 3 five bit instructions.
1 more element
A integrated circuit device comprising:
- a stack processor comprising:
- volatile memory;
- a ferroelectric random access memory;
- a data stack comprising a top portion comprising a first portion of the volatile memory and a bottom portion comprising a first portion of the ferroelectric random access memory;
- and
- a return stack comprising a top portion comprising a second portion of the volatile memory and a bottom portion comprising a second portion of the ferroelectric random access memory,
- wherein the stack processor is configured to transfer data between the data and return stacks in response to a stack-based computer programming language comprising 64 possible instructions based upon a 16 bit word, wherein each of said instructions in said 16 bit word comprises 3 five bit instructions and a 16th bit applicable to each of said 3 five bit instructions.
4 more elements
Dependencies are inferred from the claim text.