Memory devices and memory control methods with ISP code
AssigneeSilicon Motion, Inc.
InventorsWei-Lun Yan, Chun-Yi Lo
Life of this patent
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Abstract
A memory device is provided, including a first memory die, a second memory die and a controller. The first memory die has a first system block. The second memory die has a second system block. The controller is coupled to the first and second memory dies through a chip enable lane in order to write the same in-system programming codes (ISP codes) to the first and second system blocks, in which, when the memory device is turned on, the controller reads the ISP code from the first system block or the second system block.
Claims10
A memory device, comprising
- a first memory die, having a first system block;
- a second memory die, having a second system block;
- and
- a controller, coupled to the first and second memory dies through a chip enable lane in order to write the same in-system programming codes (ISP codes) to the first and second system blocks, wherein, when the memory device is turned on, the controller reads the ISP code from the first system block or the second system block.
A memory control method, suitable for a memory device having a controller and first and second memory dies respectively having first and second system blocks, comprising
- writing the same in-system programming codes (ISP codes) to the first and second system blocks;
- and
- reading the ISP code from the first system block or the second system block through a chip enable lane by the controller when the memory device is turned on.
Dependencies are inferred from the claim text.