Non-blocking processor bus bridge for network processors or the like
AssigneeLSI Corporation
InventorsRichard J. Byrne, David S. Masters
Life of this patent
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AssigneeLSI Corporation
InventorsRichard J. Byrne, David S. Masters
Estimating the term…
Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation.
In a bridge coupling between a first bus and a second bus, a method for communicating between the first and second buses comprising:
In a bridge coupling between a first bus and a second bus, a method for communicating between the first and second buses comprising:
A bridge for communicating between a first bus and a second bus, comprising:
Dependencies are inferred from the claim text.