US 8,949,493 B1 · Configurable multi-lane scrambler for flexible protocol support

Abstract

Various structures and methods are disclosed related to configurable scrambling circuitry. Embodiments can be configured to support one of a plurality of protocols. Some embodiments relate to a configurable multilane scrambler that can be adapted either to combine scrambling circuits across a plurality of lanes or to provide independent lane-based scramblers. Some embodiments are configurable to select a scrambler type. Some embodiments are configurable to adapt to one of a plurality of protocol-specific scrambling polynomials. Some embodiments relate to selecting between least significant bit (“LSB”) and most significant bit (“MSB”) ordering of data. In some embodiments, scrambler circuits in each lane are adapted to handle data that is more than one bit wide.

Claims20

Dependent claims

A configurable scrambler in an integrated circuit (“IC”) comprising:

a plurality of linear feedback shift register (“LFSR”) circuits, each coupled to receive data in one of a plurality of data lanes;
and
selection circuits coupled between the LFSR circuits, the selection circuits being configurable to select between two modes of the configurable scrambler, the two modes including:
a first mode in which each of the plurality of LFSR circuits scramble data in a corresponding lane separately and a second mode in which two or more of the LFSR circuits are combined to scramble data in two or more of the plurality of the lanes, wherein combining the LFSR circuits includes providing a scramble output of a first LFSR circuit to a scramble input of a second LFSR circuit, the first LFSR circuit being coupled to one of the plurality of lanes and the second LFSR circuit being coupled to another of the plurality of lanes.

1 more element

A scrambler comprising:

a plurality of linear feedback shift register (“LFSR”) circuits, each coupled to receive data in one of a plurality of data lanes;
a first plurality of selection circuits, a selection circuit of the first plurality of selection circuits being coupled to provide output to an LFSR circuit in one of the plurality of lanes by selecting input from one of at least two data input signals, a first data input signal of the at least two data input signals being from a first data lane of the plurality of data lanes and a second data input signal of the at least two data input signals being from a second data lane of the plurality of data lanes;
and
a second plurality of selection circuits, each coupled to provide output by selecting input from output of one of at least two of the plurality of LFSR circuits.

1 more element

Dependencies are inferred from the claim text.

Configurable multi-lane scrambler for flexible protocol support

Life of this patent

Configurable multi-lane scrambler for flexible protocol support

Life of this patent

Abstract

Claims20