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US 8,949,492 B2Granted
Apparatus including buffer allocation management and related methods
AssigneeMicron Technology, Inc.
InventorsDouglas A. Larson, Joseph M. Jeddeloh
Life of this patent
Estimating the term…
Abstract
Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.
Claims20
An apparatus, comprising:
- a number of hardware masters;
- non-volatile memory control circuitry coupled to non-volatile memory;
- volatile memory control circuitry coupled to volatile memory including a plurality of first buffers;
- and
- a switch coupled to the volatile memory control circuitry, to the non-volatile memory control circuitry, and to the number of hardware masters, wherein the switch includes:
- a plurality of second buffers distinct from the non-volatile memory and the volatile memory;
- and
- a buffer allocation management (BAM) circuit including a buffer tag pool, wherein the buffer tag pool includes a plurality of tags, each identifying a respective one of the plurality of first buffers or the plurality of second buffers, wherein the BAM circuit is configured to:
- allocate a tag to one of the number of hardware masters in response to an allocation request from the one of the number of hardware masters;
- and
- prioritize allocation of a tag identifying one of the plurality of second buffers over a tag identifying one of the plurality of first buffers;
- wherein at least one of the number of hardware masters is configured to enable direct memory access (DMA) operations between the non-volatile memory control circuitry and the volatile memory control circuitry with access to a space of the volatile memory without regard to the plurality of tags.
9 more elements
A method, comprising:
- receiving an allocation request from one of a number of hardware masters;
- allocating a tag, via a buffer allocation management (BAM) circuit including a buffer tag pool, to the one of the number of hardware masters in response to the request, wherein the buffer tag pool includes a plurality of tags, each identifying a respective one of a plurality of first buffers or a plurality of second buffers;
- prioritizing allocation of a tag identifying one of the plurality of second buffers over a tag identifying one of the plurality of first buffers;
- and
- enabling direct memory access (DMA) operations between non-volatile memory control circuitry and volatile memory control circuitry with access to a space of the volatile memory without regard to the plurality of tags, wherein the volatile memory control circuitry is coupled to volatile memory including the plurality of first buffers, and wherein the non-volatile memory control circuitry is coupled to non-volatile memory that is distinct from the plurality of second buffers.
2 more elements
An apparatus, comprising:
- a number of hardware masters;
- non-volatile memory control circuitry coupled to non-volatile memory;
- volatile memory control circuitry coupled to volatile memory including a plurality of first buffers;
- and
- a switch coupled to the volatile memory control circuitry, to the non-volatile memory control circuitry, and to the number of hardware masters, wherein the switch includes:
- a plurality of second buffers distinct from the non-volatile memory and the volatile memory;
- and
- a buffer allocation management (BAM) circuit including a buffer tag pool, wherein the buffer tag pool includes a plurality of tags, each identifying a respective one of the plurality of first buffers or the plurality of second buffers,
- wherein the BAM circuit is configured to:
- receive an allocation request in association with a read command or a write command for the non-volatile memory;
- allocate a tag to one of the number of hardware masters in response to the request;
- prioritize allocation of a tag identifying one of the plurality of second buffers over a tag identifying one of the plurality of first buffers;
- receive a request for deallocation of an allocated tag in conjunction with completion of the read command or the write command;
- and
- prioritize deallocation requests over allocation requests including prioritizing a particular request for deallocation of a second allocated tag corresponding to a first one of the plurality of second buffers over a particular allocation request corresponding to a second one of the plurality of second buffers.
12 more elements
Dependencies are inferred from the claim text.