Direct memory access to storage devices
AssigneeMellanox Technologies, Ltd.
InventorsMichael Kagan, Diego Crupnicoff
Life of this patent
Estimating the term…
Abstract
An interface device includes a first proxy interface configured to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device and a second proxy interface configured to carry out second DMA transactions initiated by a storage drive. A buffer memory is coupled between the first and second proxy interfaces and configured to temporarily hold data transferred in the first and second DMA transactions. Control logic is configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer between the I/O device and the storage drive.
Claims23
An interface device, comprising:
- a first proxy interface configured to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device;
- a second proxy interface configured to carry out second DMA transactions initiated by a storage drive,
- wherein the first and second proxy interfaces are configured to carry out the DMA transactions as bus slaves in accordance with a peripheral component interface bus standard, and
- wherein at least one of the first and second proxy interfaces is configured to be connected to a peripheral component interface bus to which both the I/O device and the storage drive are configured to be coupled;
- a buffer memory, coupled between the first and second proxy interfaces and configured to temporarily hold data transferred in the first and second DMA transactions;
- and
- control logic, configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer memory between the I/O device and the storage drive,
- wherein the control logic is configured to cause the data to be transferred between the I/O device and the storage drive without involvement of a central processing unit (CPU) and host memory that are connected to the peripheral component interface bus.
An interface device, comprising:
- at least one proxy interface, which is configured to be coupled to a peripheral component interface bus, to which a central processing unit (CPU), a host memory, and first and second input/output (I/O) devices are also coupled, and which is configured to carry out, over the bus, first direct memory access (DMA) transactions initiated by the first I/O device and second DMA transactions initiated by the second I/O device as a bus slave in accordance with a peripheral component interface bus standard;
- a buffer memory, coupled to the at least one proxy interface and configured to temporarily hold data transferred in the first and second DMA transactions;
- and
- control logic, configured to invoke the second DMA transactions in response to the first DMA transactions so as to cause the data to be transferred via the buffer memory between the first and second I/O devices without involvement of the CPU and the host memory.
A method for data transfer, comprising:
- coupling a first proxy interface to carry out first direct memory access (DMA) transactions initiated by an input/output (I/O) device;
- coupling a second proxy interface to carry out second DMA transactions initiated by a storage drive,
- wherein the first and second proxy interfaces are configured to carry out the DMA transactions as bus slaves in accordance with a peripheral component interface bus standard;
- coupling at least one of the first and second proxy interfaces to a peripheral component interface bus to which both the I/O device and the storage drive are coupled;
- invoking the second DMA transactions in response to the first DMA transactions so as to cause data to be transferred between the I/O device and the storage drive via a bus of a host computer without passing through a main memory of the host computer and without involvement of a central processing unit (CPU) and the main memory of the host computer, which are connected to the peripheral component interface bus.
Dependencies are inferred from the claim text.